1.27 mm

BOARD LAYOUT

FOR DRT PACKAGE

1.27 mm

TPD2E009DRTR AT

eSATA PORT

GND

GND VIA

D+

D–

TPD2E009

www.ti.com

SLVS953B – JUNE 2009 – REVISED AUGUST 2015

9 Power Supply Recommendations

The TPD2E009 device is a passive ESD-protection device, and therefore, does not require a power supply. Care

must be taken to avoid violating the maximum-voltage specification to ensure that the device functions properly.

The D+ and D– lines share a TVS diode that can tolerate up to 5.5 V.

10 Layout

10.1 Layout Guidelines

Layout considerations such as package selection, trace routing, and so forth, must be accounted for while

designing the ESD clamp circuit for a high-speed interface. Difficult routing can lead the designer to use vias or

stubs in the board traces, which creates significant disruption in the line impedance in the high-speed signal path.

Poor package choice can force the designer to route differential traces with unequal lengths and add the skew in

the signals. TI recommends coupling the differential traces closely to reduce the EMI interference.

The TPD2E009 can provide system-level ESD protection to the high-speed differential ports (up to 6-Gbps data

rate). The flow-through package offers flexibility for board routing with traces up to 15 mils (0.38 mm) wide.

Figure 14 and Figure 15 show the board layout scheme for the D+ and D– lines of a single differential pair, which

allows the differential signal pairs to couple together right after they touch the ESD ports (pin 1 and pin 2) of the

TPD2E009.

10.2 Layout Examples

Figure 14. TPD2E009DRTR at eSATA Connector Interface

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