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ADEMA124ACPZ Datasheet(PDF) 52 Page - Analog Devices |
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ADEMA124ACPZ Datasheet(HTML) 52 Page - Analog Devices |
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52 / 78 page  Data Sheet ADEMA124/ADEMA127 REGISTER SUMMARY analog.com Rev. A | 52 of 78 Table 27. Retained MMR Summary 14-Bit Address Name Description Default Value Access 0x001 SWRST Software Reset. 0x00 W 0x002 CONFIG0 ADC Configuration. 0xC2 R/W 0x003 TDM_STATUS Tamper Detect Status. 0x00 R/W 0x004 ADC_PD ADC Power Down. 0x00 R/W 0x005 ADC_CMI ADC Input Common-Mode Configuration. 0x00 R/W 0x006 ADC_GAIN ADC Gain Configuration. 0x00 R/W 0x007 ADC_INV ADC Input Inversion. 0x00 R/W 0x008 CONFIG_CRC_MMR_RETAINED Configuration of Background Retained Register Map CRC. 0x00 R/W 0x009 TDM_CONFIG Tamper Detect Configuration. 0x80 R/W 0x00A TDM_THRSH_MSB Tamper Detect Threshold Most Significant Bits. 0x00 R/W 0x00B TDM_THRSH_LSB Tamper Detect Threshold Least Significant Bits. 0x00 R/W 0x00E CRC_RESULT_MMR_RETAINED_HI Background Retained Register Map CRC Most Significant Byte. 0x22 R 0x00F CRC_RESULT_MMR_RETAINED_LO Background Retained Register Map CRC Least Significant Byte. 0xC7 R Note the registers in Table 28 are reset to the default value when the ADEMA124/ADEMA127 enter standby mode. For more details, see the Standby Mode section. Table 28. MMR Summary 14-Bit Address Name Description Default Value Access 0x010 EFUSE_REFRESH EFuse Refresh. 0x00 R/W 0x012 ACCESS_EXTENDED_MMAP Extended Memory Map Access Control. 0x00 R/W 0x013 SCRATCH Software Debug Register. 0x00 R/W 0x014 SYNC_SNAP ADC Synchronization Control. 0x00 R/W 0x017 SNAPSHOT_COUNT_HI System Timing Controller Counter. 0x00 R 0x018 SNAPSHOT_COUNT_LO System Timing Controller Counter. 0x00 R 0x019 MASK0 High Priority Interrupt Mask. 0x00 R/W 0x01A MASK1 Lower Priority Interrupt Mask. 0x00 R/W 0x01B MASK2 DSP Interrupt Mask. 0x08 R/W 0x01F WR_LOCK Configuration Lock. 0x5E R/W 0x020 STATUS0 Latched Status of High Priority Interrupts. 0x00 R/W 0x021 STATUS1 Latched Status of Lower Priority Interrupts. 0x00 R/W 0x022 STATUS2 DSP Status. 0x01 R/W 0x025 CONFIG_CRC_MMR Configuration of Background Register Map CRC. 0x00 R/W 0x026 V0_WAV_HI ADC Channel 0 Waveform Data Most Significant Byte. 0x00 R/W 0x027 V0_WAV_MD ADC Channel 0 Waveform Data Middle Byte. 0x00 R/W 0x028 V0_WAV_LO ADC Channel 0 Waveform Data Least Significant Byte. 0x00 R/W 0x029 V1_WAV_HI ADC Channel 1 Waveform Data Most Significant Byte. 0x00 R/W 0x02A V1_WAV_MD ADC Channel 1 Waveform Data Middle Byte. 0x00 R/W 0x02B V1_WAV_LO ADC Channel 1 Waveform Data Least Significant Byte. 0x00 R/W 0x02C V2_WAV_HI ADC Channel 2 Waveform Data Most Significant Byte. 0x00 R/W 0x02D V2_WAV_MD ADC Channel 2 Waveform Data Middle Byte. 0x00 R/W 0x02E V2_WAV_LO ADC Channel 2 Waveform Data Least Significant Byte. 0x00 R/W 0x02F V3_WAV_HI ADC Channel 3 Waveform Data Most Significant Byte. 0x00 R/W 0x030 V3_WAV_MD ADC Channel 3 Waveform Data Middle Byte. 0x00 R/W 0x031 V3_WAV_LO ADC Channel 3 Waveform Data Least Significant Byte. 0x00 R/W 0x032 V4_WAV_HI ADC Channel 4 Waveform Data Most Significant Byte. 0x00 R/W 0x033 V4_WAV_MD ADC Channel 4 Waveform Data Middle Byte. 0x00 R/W |
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