ADEMA124ACPZ datasheet(21/78 Pages) AD

21 / 78 page

Data Sheet

ADEMA124/ADEMA127

APPLICATIONS INFORMATION

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Rev. A | 21 of 78

START-UP SEQUENCE AND TIMING

Fast Start-Up

The ADEMA124/ADEMA127 immediately start sampling and pro-

ducing waveform data once a valid power supply is present. The

ADC must be provided with a valid clock input signal or have an

external crystal present and neither the RESET pin nor STDBY pin

asserted.

Start-up is shown in Figure 39. Fast start-up time is defined as

the time between VDD supply reaching the minimum valid supply

level and first data samples being available. The first low-to-high

transition of the DREADY pin indicates the SPI port is available for

communication. The first high-to-low transition of the DREADY pin

indicates the first ADC sample set is available. The first SPI read

returns 0x00 for all ADC waveform data. If the first ADC sample

set is required, read the SPI port on the first DREADY pin rising

edge. The first set of ADC samples is then available to be read

on the first DREADY pin high-to-low transition. The first two ADC

wavefrom data sets pass through the lower latency sinc1 filter with

a decimation factor of 64.

The ADEMA124/ADEMA127 provide valid ADC samples in less

than 0.5ms when provided an external clock from the time that

VDD is at 90% (tSTART-UP). Valid ADC samples are generated with

15ms when the ADEMA124/ADEMA127 must first start the crystal

oscillator circuit to generate a clock from an external crystal.

Figure 39. Fast Start-Up Timing

ADEMA124ACPZ Datasheet(PDF) 21 Page - Analog Devices