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TPS73033DBVT Datasheet(PDF) 3 Page - Texas Instruments |
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TPS73033DBVT Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 43 page ![]() 4 Pin Configuration and Functions IN GND EN OUT NC/NR 1 2 3 5 4 Figure 4-1. DBV Package, 5-Pin SOT-23 Fixed- Voltage Version (Top View) IN GND EN OUT NC/NR 1 2 3 6 4 5 FB Figure 4-2. DBV Package, 6-Pin SOT-23 Adjustable- Voltage Version (Top View) A3 A1 C3 C1 B2 IN OUT GND NR EN Figure 4-3. YZQ Package, 5-Pin DSBGA (Top View, Legacy Chip) Table 4-1. Pin Functions PIN I/O DESCRIPTION NAME DBV YZQ EN 3 A3 I Enable pin. Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. EN can be connected to IN if not used. FB 5 — I Feedback pin. This terminal is the feedback input pin for the adjustable device. Fixed voltage versions in the DBV package do not have this pin. GND 2 A1 — Regulator ground. IN 1 C3 I Input to the device. NC/NR 4 B2 — Noise-reduction pin (legacy chip). Connecting an external capacitor to this pin filters noise generated by the internal band gap. This configuration improves power-supply rejection and reduces output noise for the legacy chip and YZQ package. No connect pin (new chip). This pin is not internally connected. Connect to GND for improved thermal performance or leave floating. For lower noise performance on a fixed device, refer to the TPS7A20. For lower noise performance on the adjustable version, consider using a feed-forward capacitor. OUT 6 C1 O Output of the regulator. www.ti.com TPS730 SBVS054K – NOVEMBER 2004 – REVISED JUNE 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS730 |
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