5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN

MAX

UNIT

Voltage

VIN , VEN, VOUT (legacy chip)

–0.3

6

V

VIN , VEN (new chip)

–0.3

6.5

V

VOUT (new chip)

–0.3

VIN + 0.3 (2)

Current

Output, IOUT

Internally limited

Temperature

Operating junction, TJ (DBV package)

–40

150

°C

Operating junction, TJ (YZQ package, legacy chip only)

–40

125

°C

Storage, Tstg

–65

150

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2)

The absolute maximum rating is VIN + 0.3 V or 6.5 V, whichever is smaller.

5.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001,

all pins(1)

±2000

V

Charged device model (CDM), per JEDEC specification

JESD22-C101, V all pins(2)

±500

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VIN

Input voltage

2.7

5.5

V

VEN

Enable voltage

0

5.5

V

VOUT

Output voltage

VFB

5

V

IOUT

Output current

0

200

mA

TJ

Operating junction temperature

–40

125

°C

CIN

Input capacitor (legacy chip)

0.1

1

µF

Input capacitor (new chip)

1

COUT

Output capacitor

2.2(1) (2)

10

µF

CNR

Noise reduction capacitor(3)

0

10

nF

CFF

Feed-forward capacitor (legacy chip)

15

pF

Feed-forward capacitor (new chip)(4)

0

10

100

nF

R2

Lower feedback resistor (legacy chip)

30.1

kΩ

FEN

Enable toggle frequency (new chip)

10

kHz

(1)

If CFF is not used or VOUT(nom) < 1.8V, the minimum recommended COUT = 4.7µF.

(2)

The minimum effective capacitance is 0.47 µF for the new chip only.

(3)

Legacy chip only. The new chip does not have a Noise Reduction pin. For more information please refer to Pin Functions table.

(4)

Feed-forward capacitor is optional and not required for stability.

TPS730

SBVS054K – NOVEMBER 2004 – REVISED JUNE 2025

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