5.5 Electrical Characteristics (continued)

over recommended operating temperature range, TJ = –40°C to +125°C VEN = VIN, VIN = VOUT(nom) + 1V, IOUT = 1mA, COUT =

10µF, CNR = 0.01µF (unless otherwise noted). All typical values at TJ= 25°C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PSRR

Power-supply

rejection ratio

f = 100Hz

IOUT = 10mA

(legacy chip)

70

dB

IOUT = 10mA

(new chip)

64

IOUT = 200mA

(legacy chip)

68

IOUT = 200mA

(new chip)

65

f = 10kHz

IOUT = 200mA

(legacy chip)

70

IOUT = 200mA

(new chip)

49

f = 100kHz

IOUT = 200mA

(legacy chip)

43

IOUT = 200mA

(new chip)

39

Vn

Output noise

voltage

BW = 200Hz to

100kHz, IOUT =

200mA

CNR = 0.01µF

33

µVRMS

BW = 200Hz to

100kHz, IOUT =

200mA

(new chip)(4)

69

tSTR

Time, start-up

RL = 14 Ω,

COUT = 1µF

CNR = 0.001µF

50

µs

CNR = 0.0047µF

50

CNR = 0.01µF

50

(new chip)(4)

500

VEN(HI)

High-level

enable input

voltage

2.7V ≤ VIN ≤ 5.5V

1.7

VIN

V

2.7V ≤ VIN ≤ 5.5V (new chip)

0.85

VIN

VEN(LOW)

Low-level

enable input

voltage

2.7V ≤ VIN ≤ 5.5V

0

0.7

V

2.7V ≤ VIN ≤ 5.5V (new chip)

0

0.425

IEN

Enable pin

current

VEN = 0 V

–1

1

µA

VUVLO

UVLO threshold

VIN rising (legacy chip)

2.25

2.65

V

VIN rising (new chip)

1.32

1.6

VUVLO(HYST)

UVLO

hysteresis

VCC rising (legacy chip)

100

mV

VCC rising (new chip)

130

(1)

Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.

(2)

Dropout is not measured for the TPS73018 and TPS73025 because minimum VIN = 2.7V.

(3)

For adjustable versions, this parameters applies only after VIN is applied; then VEN transitions high to low.

(4)

New Chip does not have a Noise Reduction pin.

TPS730

SBVS054K – NOVEMBER 2004 – REVISED JUNE 2025

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