8.2.3 Application Curves

Time ( 10 ) (s)

x

–9

0.5

–0.5

0.4

0.4

1.0

1.6

–0.4

0.3

–0.3

0.2

0.2

0.8

1.4

2.0

–0.2

0.1

–0.1

0.0

0.0

0.6

1.2

1.8

Figure 8-2. Eye Pattern: 480Mbps USB Signal With

No Switch (Through Path)

Time ( 10 ) (s)

x

–9

0.5

–0.5

0.4

0.4

1.0

1.6

–0.4

0.3

–0.3

0.2

0.2

0.8

1.4

2.0

–0.2

0.1

–0.1

0.0

0.0

0.6

1.2

1.8

Figure 8-3. Eye Pattern: 480Mbps USB Signal With

Switch NC Path

Time ( 10 ) (s)

x

–9

0.5

–0.5

0.4

0.4

1.0

1.6

–0.4

0.3

–0.3

0.2

0.2

0.8

1.4

2.0

–0.2

0.1

–0.1

0.0

0.0

0.6

1.2

1.8

Figure 8-4. Eye Pattern: 480Mbps USB Signal With Switch NO Path

8.3 Power Supply Recommendations

Power to the device is supplied through the VCC pin and must follow the USB 1.0, 1.1, and 2.0 standards. TI

recommends placing a bypass capacitor as close as possible to the supply pin VCC to help smooth out lower

frequency noise to provide better load regulation across the frequency spectrum.

8.4 Layout

8.4.1 Layout Guidelines

Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the D+

and D– traces.

The high-speed D+ and D– traces must always be of equal length and must be no more than 4 inches;

otherwise, the eye diagram performance may be degraded. A high-speed USB connection is made through a

shielded, twisted pair cable with a differential characteristic impedance. In the layout, make sure the impedance

of D+ and D– traces match the cable characteristic differential impedance for optimal performance.

Route the high-speed USB signals using a minimum of vias and corners to reduce signal reflections and

impedance changes. When a via must be used, increase the clearance size around the via to minimize the

TS3USB30E

SCDS255G – DECEMBER 2008 – REVISED OCTOBER 2024

www.ti.com

14

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