TUSB1210 datasheet(4/72 Pages) TI2

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5 Pin Configuration and Functions

REFCLK

N/C

NXT

DATA0

VBUS

DATA1

VBAT

DATA2

VDD33

DATA3

DATA4

N/C

CPEN

Not to scale

GND

Figure 5-1. RHB Package Top View

Table 5-1. Pin Functions

A/D

TYPE

LEVEL

DESCRIPTION

NAME

NO.

CFG

VDDIO

REFCLK clock frequency configuration pin. Two frequencies are supported: 19.2 MHz

when 0, or 26 MHz when 1.

CLOCK

VDDIO

ULPI 60 MHz clock on which ULPI data is synchronized.

Two modes are possible:

Input Mode: CLOCK defaults as an input.

Output Mode: When an input clock is detected on REFCLK pin (after 4 rising edges)

then CLOCK will change to an output.

CPEN

VDD33

CMOS active-high digital output control of external 5 V VBUS supply

VDDIO

Active-high chip select pin. When low the IC is in power down and ULPI bus is

tri-stated. When high normal operation. Tie to VDDIO if unused.

DATA0

I/O

VDDIO

ULPI DATA input or output signal 0 synchronized to CLOCK

DATA1

I/O

VDDIO

ULPI DATA input or output signal 1 synchronized to CLOCK

DATA2

I/O

VDDIO

ULPI DATA input or output signal 2 synchronized to CLOCK

DATA3

I/O

VDDIO

ULPI DATA input or output signal 3 synchronized to CLOCK

DATA4

I/O

VDDIO

ULPI DATA input or output signal 4 synchronized to CLOCK

DATA5

I/O

VDDIO

ULPI DATA input or output signal 5 synchronized to CLOCK

DATA6

I/O

VDDIO

ULPI DATA input or output signal 6 synchronized to CLOCK

DATA7

I/O

VDDIO

ULPI DATA input or output signal 7 synchronized to CLOCK

DIR

VDDIO

ULPI DIR output signal

I/O

VDD33

DM pin of the USB connector

I/O

VDD33

DP pin of the USB connector

I/O

VDD33

Identification (ID) pin of the USB connector

N/C

8, 15,16,

24, 25

—

No connection

TUSB1210

SLLSE09J – NOVEMBER 2009 – REVISED JULY 2021

www.ti.com

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