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DM505LRBABF Datasheet(PDF) 25 Page - Texas Instruments |
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DM505LRBABF Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 295 page ![]() Copyright © 2016–2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback 25 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Table 4-1. Pin Attributes(1) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MUXMODE [8] I/O VOLTAGE VALUE [9] POWER [10] HYS [11] BUFFER TYPE [12] PULL UP/DOWN TYPE [13] DSIS [14] E14 uart1_txd uart1_txd 0 O PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD spi4_d0 4 IO 0 gpmc_a13 10 O mcan_rx 12 IO 1 gpio4_14 14 IO Driver off 15 I F15 uart2_ctsn uart2_ctsn 0 I OFF OFF 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1 xref_clk1 2 I gpmc_a18 3 O spi3_sclk 4 IO 0 qspi1_cs1 5 IO 1 timer7 6 IO vin2a_hsync0 9 I gpmc_clk 10 IO 0 mcan_tx 12 IO 1 gpio4_19 14 IO Driver off 15 I F16 uart2_rtsn uart2_rtsn 0 O PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD eCAP1_in_PWM1_out 1 IO 0 gpmc_a19 3 O spi3_cs0 4 IO 1 timer8 6 IO vin2a_vsync0 9 I mcan_rx 12 IO 1 gpio4_20 14 IO Driver off 15 I D14 uart2_rxd uart2_rxd 0 I PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1 spi3_d1 4 IO 0 timer1 6 IO ehrpwm1A 7 O gpmc_clk 10 IO 0 gpmc_a12 11 O dcan1_tx 12 IO gpio4_17 14 IO Driver off 15 I |
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