DM505LRBABF datasheet(45/295 Pages) TI2

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DM505

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SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Terminal Configuration and Functions

4.3.7

CSI2

NOTE

For more information, see the Imaging Subsystem of the Device TRM.

CAUTION

The IO timings provided in Section 5.9 Timing Requirements and Switching

Characteristics are only valid if signals within a single IOSET are used. The

IOSETs are defined in Table 5-32.

Table 4-8. CSI 2 Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

csi2_0_dx0

Serial Differential data/clock positive input - lane 0 (position 1)

A11

csi2_0_dy0

Serial Differential data/clock negative input - lane 0 (position 1)

B11

csi2_0_dx1

Serial Differential data/clock positive input - lane 1 (position 2)

A12

csi2_0_dy1

Serial Differential data/clock negative input - lane 1 (position 2)

B12

csi2_0_dx2

Serial Differential data/clock positive input - lane 2 (position 3)

A13

csi2_0_dy2

Serial Differential data/clock negative input - lane 2 (position 3)

B13

csi2_0_dx3

Serial Differential data/clock positive input - lane 3 (position 4)

A15

csi2_0_dy3

Serial Differential data/clock negative input - lane 3 (position 4)

B15

csi2_0_dx4

Serial Differential data positive input only - lane 4 (position 5) (1)

A16

csi2_0_dy4

Serial Differential data negative input only - lane 4 (position 5) (1)

B16

(1) Lane 4 (position 5) supports only data. For more information see Imaging Subsystem of the Device TRM.

4.3.8

EMIF

NOTE

For more information, see the Memory Subsystem / EMIF Controller section of the Device

TRM.

NOTE

The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in Table 4-9,

EMIF Signal Descriptions, column "SIGNAL NAME" is not to be confused with DDR1 type of

SDRAM memories.

Table 4-9. EMIF Signal Descriptions

SIGNAL NAME

DESCRIPTION

TYPE

BALL

ddr1_cke0

EMIF1 Clock Enable 0

ddr1_nck

EMIF1 Negative Clock

ddr1_odt0

EMIF1 On-Die Termination for Chip Select 0

ddr1_rasn

EMIF1 Row Address Strobe; When LPDDR2 is used this signal functions as to

ddr1_ca0

ddr1_rst

EMIF1 Reset output

ddr1_wen

EMIF1 Write Enable; When LPDDR2 is used this signal functions as ddr1_ca2

ddr1_csn0

EMIF1 Chip Select 0

ddr1_ck

EMIF1 Clock

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