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CY28301PVC Datasheet(PDF) 11 Page - SpectraLinear Inc

Part # CY28301PVC
Description  Frequency Generator for Intel(r) Integrated Chipset
PDF  13 Pages
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Manufacturer  SPECTRALINEAR [SpectraLinear Inc]
Direct Link  http://www.spectralinear.com
Logo SPECTRALINEAR - SpectraLinear Inc

CY28301PVC Datasheet(HTML) 11 Page - SpectraLinear Inc

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CY28301
Rev 1.0, November 27, 2006
Page 11 of 13
Cin
Input Pin Capacitance
5
pF
Cxtal
Xtal Pin Capacitance
13.5
22.5
pF
Cout
Output Pin Capacitance
6
pF
Lpin
Pin Inductance
0
7
nH
Ta
Ambient Temperature
No airflow
0
70
°C
DC Operating Requirements (continued)
Parameter
Description
Condition
Min.
Max.
Unit
AC Electrical Characteristics[2] (TA = 0°C to +70°C, VDDQ3 = 3.3V ±5%, VDDQ2= 2.5V ±5% fXTL = 14.31818 MHz)
Parameter
Description
66.6-MHz Host
100-MHz Host
133-MHz Host
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
CPUCLK
TPeriod
Host/CPUCLK Period
15.0
15.5
10.0
10.5
7.5
8.0
ns
4
THIGH
Host/CPUCLK High Time
5.2
N/A
3.0
N/A
1.87
N/A
ns
5
TLOW
Host/CPUCLK Low Time
5.0
N/A
2.8
N/A
1.67
N/A
ns
6
TRISE
Host/CPUCLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
Host/CPUCLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
SDRAM
TPeriod
SDRAM CLK Period
10.0
10.5
10.0
10.5
10.0
10.5
ns
4
THIGH
SDRAM CLK High Time
3.0
N/A
3.0
N/A
3.0
N/A
ns
5
TLOW
SDRAM CLK Low Time
2.8
N/A
2.8
N/A
2.8
N/A
ns
6
TRISE
SDRAM CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
SDRAM CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
APIC
TPeriod
APIC CLK Period
60.0
64.0
60.0
N/A
60.0
64.0
ns
4
THIGH
APIC CLK High Time
25.5
N/A
25.5
N/A
25.5
N/A
ns
5
TLOW
APIC CLK Low Time
25.3
N/A
25.30
N/A
25.30
N/A
ns
6
TRISE
APIC CLK Rise Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
TFALL
APIC CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
ns
3V66
TPeriod
3V66 CLK Period
15.0
16.0
15.0
16.0
15.0
16.0
ns
4, 8
THIGH
3V66 CLK High Time
5.25
N/A
5.25
N/A
5.25
N/A
ns
5
TLOW
3V66 CLK Low Time
5.05
N/A
5.05
N/A
5.05
N/A
ns
6
TRISE
3V66 CLK Rise Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
TFALL
3V66 CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
ns
Notes:
4. Period, jitter, offset, and skew measured on the rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
5. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable and
operating within specifications.
6. TRISE and TFALL are measured as transitions through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification.
7. THIGH is measured at 2.0V for 2.5V outputs, and 2.4V for 3.3V outputs.
8. TLOW is measured at 0.4V for all outputs.



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