CY28301

Rev 1.0, November 27, 2006

Page 5 of 13

CY28301 Serial Configuration Map

1. The serial bits will be read by the clock driver in the following

order:

Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0

2. All unused register bits (reserved and N/A) should be

written to a “0” level.

3. All register bits labeled “Initialize to 0" must be written to “0”

during initialization.

Byte 0: Control Register 0

Bit

Pin#

Name

Default

Description

Bit 7

–

SEL1

0

See 5

Bit 6

–

SEL0

0

See 5

Bit 5

–

Reserved

0

Reserved

Bit 4

–

Reserved

0

Reserved

Bit 3

–

FS_Override

0

0 = Select operating frequency by FS[1:0] input pins

1 = Select operating frequency by SEL[1:0] settings

Bit 2

–

Spread Select2

0

‘000’ = Normal (spread off)

‘001’ = Test mode

‘010’ = Reserved

‘011’ = Three-stated

‘100’ = –0.5%

‘101’ = –0.75%

‘110’ = –1.0%

‘111’ = –0.3%

Bit 1

–

Spread Select1

0

Bit 0

–

Spread Select0

0

Byte 1: Control Register 1

Bit

Pin#

Name

Default

Description

Bit 7

56

Latched FS1 input

X

Latched FS[1:0] inputs. These bits are Read-only.

Bit 6

34

Latched FS0 input

X

Bit 5

–

Reserved

0

Reserved

Bit 4

–

Reserved

0

Reserved

Bit 3

–

Reserved

0

Reserved

Bit 2

–

Reserved

0

Reserved

Bit 1

56

REF

1

(Active/Inactive)

Bit 0

56

REF_DRV

0

REF Clock output drive strength

0 = Normal

1= High drive