L6260 datasheet(17/30 Pages) STMICROELECTRONICS

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The duration of the brake delay is defined by an

external resistor and capacitor connected to the

brake delay pin (BRK_DLY). Charge stored in an

external capacitor connected to the Voltage Tri-

pler (VPDOWN) is used to supply the brake delay

circuit after the loss of power.

During the application of power to the IC, the

power on reset signal (POR) is asserted, forcing

all registers to their default state (see @POR col-

umn of the register definitions) and disabling the

VCM and spindle drivers. Once the supply volt-

age has exceeded the Voltage Good (VGT)

threshold, the POR delay begins. When this delay

has expired, POR is de-asserted. It is this delay

whose duration is determined by an external ca-

pacitor connected to the POR_DLY pin.

When a low voltage condition is detected (the

supply voltage falls below the VGT) the following

happens (in order):

Internal registers are reset and POR is as-

serted.

2) The automatic parking of the actuator is en-

abled and the brake delay starts.

3) After the brake delay expires, all low side driv-

ers are enabled to brake the spindle.

Serial Interface

The serial interface is designed to be compatible

with the Intel 80196 (and other similar micros) se-

rial interface but is capable of faster data rates,

up to 10 MHz. All read and write operations must

consist of 16 bits, with the 80196 this would be

two 8 bit accesses. The first four bits are address

and the next 12 are data. If the address is a read

the system to shift out 12 bits of data from the ad-

dressed register. The system must provide 16

SCLK pulses to insure that the read operation

completes.

SYMBOL

DESCRIPTION

MIN.

TYP.

MAX.

UNITS

tRWS

R/W setup time to SCLK going high

100

tSLS

SLOAD setup time to SCLK going high

100

tRWH

R/W hold time after SCLK going high

100

tSLH

SLOAD hold time after SCLK going high

100

tSCKD

SCLK high to Data Valid

tRWD

R/W High to Data Valid

Data bit D[0] valid from HiZ

tAS

Address setup time to SCLK going high

tDS

Data setup time to SCLK going High

tAH

Address Hold after SCLK going high

tDH

Data Hold time after SCLK going High

tSDZ

SDIO tri-state after SLOAD going High

tRWZ

SDIO tri-state after R/W going low

tPER

Minimum SCLK period

100

tREC (*)

Recycle - Time between successive accesses

100

(*) For 10MHz system clock operation (in other words. 1 or more clock cycles of SCLK).

Serial Interface Truth Table

R/W

SLOAD

SDIO

DIRECTION

Tri-state (Port unselected)

Tri-state

Tri-state (Port unselected)

Tri-state

Address/Data input

Input

Data output

Output

L6260

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