10

FN7490.4

February 14, 2008

FIGURE 37. EL8170 - SLEW RATE vs TEMPERATURE,

INPUT ±0.015V @ GAIN + 100

FIGURE 38. EL8173 - SLEW RATE vs TEMPERATURE,

INPUT ±0.015V @ GAIN + 100

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

MIN

MAX

N = 2000

MEDIAN

-40

-20

0

20406080

100

120

TEMPERATURE (°C)

0.40

0.45

0.50

0.55

0.60

0.65

0.70

MIN

MAX

N = 1000

MEDIAN

Pin Descriptions

EL8170, EL8173

PIN NAME

EQUIVALENT CIRCUIT

PIN FUNCTION

1EN

Circuit 2

Active LOW logic pins. When pulled above 2V, the corresponding channel turns off

and OUT is high impedance. A channel is enabled when pulled below 0.8V. Built-in

pull downs define each EN pin LOW when left floating.

2

IN-

Circuit 1A, Circuit 1B

High impedance input terminals. EL8170 input circuit is shown in Circuit 1A, and

the EL8173 input circuit is shown in Circuit 1B. EL8173: to avoid offset drift, it is

recommended that the terminals are not overdriven beyond 1V and the input

current must never exceed 5mA.

3

IN+

Circuit 1A, Circuit 1B

4

V-

Circuit 4

Negative supply terminal.

5

FB-

Circuit 1A, Circuit 1B

High impedance feedback terminals. EL8170 input circuit is shown in Circuit 1A,

and the EL8173 input circuit is shown in Circuit 1B. EL8173: to avoid offset drift, it

is recommended that the terminals are not overdriven beyond 1V and the input

current must never exceed 5mA.

8

FB+

Circuit 1A, Circuit 1B

7

V+

Circuit 4

Positive supply terminal.

6

VOUT

Circuit 3

Output Voltage.

IN-

V+

V-

LOGIC

PIN

V+

V-

V+

V-

OUT

CIRCUIT 3

CIRCUIT 1A

CIRCUIT 2

V+

V-

CAPACITIVELY

COUPLED

ESD CLAMP

CIRCUIT 4

V+

V-

CIRCUIT 1B

FB-

IN-

FB-

IN+

FB+

IN+

FB+

EL8170, EL8173