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L7250 Datasheet(PDF) 15 Page - STMicroelectronics |
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L7250 Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 46 page  15/46 L7250 1.4 Inverted clock serial port timing Table Symbol Parameter Min Max Unit Tcc Serial clock period 30 ns Tch Serial clock high time 13 ns Tcl Serial clock low time 13 ns Tcds Serial data setup time to clock falling edge (write mode) 5 ns Tcdh Serial clock falling edge to serial data hold time (write mode) 4 ns Tedh Serial clock falling edge to serial data hold time (read mode) 5 ns Tvld Serial clock rising edge to SDATA stable time (read mode) Cload=5pF (see Note2) Cload=50pF (see Note2) 11 15 ns ns Tel Serial Enable low time 490 ns Teh Serial Enable high time 30 ns Tefcr Serial Enable falling edge to serial clock rising edge 17 ns Tcrer Serial clock rising edge to Serial enable rising edge 17 ns Tdly SDATA turn around delay time 0 ns Note 1: All specifications with respect to 50% of signal switching thresholds Note 2: In reading mode the clock frequency is limited by this parameter; in fact the min ‘serial clock high time’ is defined by (Tvld+Tasu) where Tasu = min ASIC setup time |
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