LAN8818DSLASHKDX datasheet(59/101 Pages) MICROCHIP

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LAN8818D

DS00005832C-page 59

5.16

MIIM (MDIO) Interface

The device supports the IEEE 802.3 MII management interface, also known as the Management Data Input/Output

(MDIO) interface. This interface allows upper-layer devices to monitor and control the state of the device. An external

device with MIIM capability is used to read the PHY status and/or configure the PHY settings. More details about the

MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification [1].

The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).

• A specific protocol that operates across the physical connection mentioned earlier, which allows an external con-

troller to communicate with one or more devices. Each device is assigned a unique PHY address between 0h and

1Fh by the PHYAD[4:0] strapping pins. Refer to Section 3.3.2, "PHY Address (PHYAD[4:0])" for additional infor-

mation.

• A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indi-

rect access to MMD addresses and registers.

Table 5-7 shows the MII management frame format for the device.

5.16.1

HIGH-SPEED MDIO OPERATION

The MDIO bus can operate at standard speeds up to 2.5 MHz, as well as higher speeds up to 25 MHz. Default register

values enable standard MDIO operation using open-drain MDIO drivers, which is MDIO operation up to 2.5 MHz MDC

frequency with daisy-chained PHYs on the MDIO bus. Due to open-drain drivers, an external 1 kΩ pull-up resistor is

required.

Higher speed MDIO operation up to 25 MHz is supportable but requires reconfiguring the device to use push-pull MDIO

drivers, and does not allow daisy-chaining PHYs on the MDIO bus. The reconfiguration process requires initially running

the MDIO bus at 2.5 MHz using open-drain MDIO drivers and the external 1 kΩ pull-up resistor. The push-pull MDIO

drivers allow operation up to 25 MHz with the 1 kΩ pull-up resistor.

5.16.2

ALL PHYS ADDRESS

Normally, the Ethernet PHYs are accessed at the PHY addresses set by the PHYAD[4:0] strapping pins.

PHY Address 0h is optionally supported as the broadcast PHY address, which allows for a single write command to

simultaneously program an identical PHY register for two or more PHY devices (for example, using PHY Address 0h to

set the Basic Control register to a value of 0x1940 to set bit[11] to a value of one to enable software power-down).

PHY Address 0 is enabled (in addition to the PHY address set by the PHYAD[4:0] strapping pins) when the All-PHYAD

Enable bit in the Common Control register is set to ‘1’.

5.16.3

MDIO OUTPUT DRIVE MODE

The MDIO output pin drive mode is controlled by the MDIO Buffer Type bit in the Output Control register. When set to

a ‘0’, the MDIO output is open-drain. When set to ‘1’, the MDIO output is push-pull.

TABLE 5-7:

MII MANAGEMENT FRAME FORMAT

Preamble

Start of

Frame

Read/Write

OP Code

PHY

Address

Bits[4:0]

REG

Address

Bits[4:0]

Data Bits[15:0]

Idle

Read

32 1’s

AAAAA

RRRRR

DDDDDDDD_DDDDDDDD

Write

32 1’s

AAAAA

RRRRR

DDDDDDDD_DDDDDDDD

Note:

This device may respond to Clause 45 accesses and so must not be mixed with Clause 45 devices on the

same MDIO bus.

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