AD4083BBCZ datasheet(24/94 Pages) AD

24 / 94 page

Data Sheet

AD4083

THEORY OF OPERATION

analog.com

Rev. 0 | 24 of 94

Figure 40. Power Supply Sequence, Internally Generated IOVDD, VDD11

Figure 41. Power Supply Sequence, Externally Generated IOVDD, VDD11

POWER SAVING OPERATING MODES

The operating mode of the AD4083 is controlled by the OPERAT-

ING_MODES bits in the device configuration register (see the De-

vice Configuration Register section, Address (0x02)). On power-up

and after reset, the default is normal mode (OPERATING_MODES

= 00). Table 11 describes all operating modes, and Figure 42

depicts the allowed transitions between these modes. Note that

direct transitions between the two power saving modes (standby

mode and sleep mode) are not permitted.

It is important to stop all conversion and data interface clocking

before configuring the power mode.

When in either standby mode or sleep mode, the VDD33 supply

can be removed to reduce power consumption. This supply must

be re-established prior to issuing the SPI configuration interface

command to exit either power saving mode.

Figure 42. Operating Mode Transitions

Transitioning from normal mode to either of the two power saving

modes is achieved by writing the required value to the OPERAT-

ING_MODES bits in the device configuration register (see the

Device Configuration Register section). Waking up (that is, transi-

AD4083BBCZ Datasheet(PDF) 24 Page - Analog Devices