AD4083BBCZ datasheet(26/94 Pages) AD

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Data Sheet

AD4083

THEORY OF OPERATION

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Rev. 0 | 26 of 94

Table 11. Power Saving Operating Modes (Continued)

Operating

Mode

OPERATING_MODES

Bits Value

Description

Effect

Wake-Up Time (Maximum Time to

Normal Mode)

configuration register (see the Device Configuration

(see the Interface Configuration A Register section) are

allowed.

If IOVDD is externally supplied, all GPIOx and SPI data

interface signals are enabled. The SPI configuration

interface is fully enabled. Because the SPI data

interface remains enabled, the user can access data

in the result FIFO (see the Result FIFO section).

The ADC core is powered down. The analog circuitry

remains in reset (ANA_RESET remains asserted), and

no ADC conversions can be performed.

The VDD33 supply can be removed to reduce power.

The internal reference buffer is disabled.

When enabled, the internal VDD11 LDO regulator

remains on.

The common-mode output buffer is disabled.

The LVDS interface is disabled.

The SPI data interface remains enabled to access data

in the result FIFO (see the Result FIFO section).

To avoid device damage additional recovery time has to be added

when coming out of the standby or sleep mode. This time is

required from the time when part is back to normal mode and is

counted until the next conversion clock as indicated on the plot

Figure 43.

Figure 43. Recovery Time After Standby/Sleep Mode

SOFTWARE RESET

This reset method must only be used once the AD4083 is in an idle

state, where conversions are not being clocked, and any existing

conversion is completed.

A software reset is achieved by issuing the following two writes to

the Interface Configuration A register (see the Interface Configura-

tion A Register section, Address 0x00):

1. Set SW_RESET and SW_RESETX bits to 1 by writing 0x81 to

the register.

2. Then, issue another write command that sets either or both of

those bits to 0 to initiate the reset.

3. Software reset initialization will require 300μs. During this ini-

tialization time, reading the NOT_READY_ERR in the INTER-

FACE_STATUS_A register will return a 1 until the initialization is

complete. Once the software reset initialization is complete, the

part is now reset and NOT_READY_ERR will return to 0. SPI

configuration writes will be ignored while during this initialization

when NOT_READY_ERR is set to 1.

This action returns any previously configured registers to their de-

fault settings, except for the ADDR_ASCENSION bit from the Inter-

face Configuration A register, which keeps its previous value. The

contents of the FIFO, if any, are also not affected by the software

reset. The ADDR_ASCENSION bit and FIFO data only return to

their default settings after a hardware reset or a full power-up hap-

pens. The NOT_READY_ERR flag of the INTERFACE_STATUS_A

software reset bits (SW_RESET & SW_RESETX) is breached.

AD4083BBCZ Datasheet(PDF) 26 Page - Analog Devices

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