AD4083BBCZ datasheet(25/94 Pages) AD

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Data Sheet

AD4083

THEORY OF OPERATION

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tioning back to normal mode) is achieved in a similar way, because

the SPI configuration interface operation is not affected by any

of the power saving modes (see the SPI Configuration Interface

section). Standby mode can be selected to save power in the case

where the user wants to quickly return to normal conversions. Sleep

mode is a lower power state where returning to normal mode takes

longer. Both standby and sleep mode can be particularly useful

when used with the result FIFO (see the Result FIFO section),

whereby previously stored conversion data can be accessed from

the FIFO while it is still in the selected power saving mode.

To reduce power consumption in both standby and sleep modes,

the internal IOVDD LDO regulator is powered down. If the user

is not externally supplying IOVDD, all IOVDD domain inputs and

outputs are disabled (all GPIOx, all LVDS data interface (see the

LVDS Data Interface section), and SPI data interface (see the

SPI Data Interface section) signals are disabled. In this specific

condition, it is still possible to write to the AD4083 SPI configuration

to issue a command to return to normal mode by writing to the

OPERATING_MODES bits in the device configuration register (see

the Device Configuration Register section) or to issue a software

reset (see the Software Reset section). As GPIOx is disabled, it is

not possible to perform any read activity on the SPI configuration

interface bus.

When IOVDD is externally supplied, and the device is put into

standby or sleep mode, the LVDS data interface is disabled; howev-

er, all GPIOx, SPI data interface, and SPI configuration interface

pins remain enabled and unaffected. While power is supplied exter-

nally to IOVDD within its specified range, previously acquired data

stored in the result FIFO can be access in either standby or sleep

mode.

Table 11 also indicates the wake-up times associated with each of

the modes. Wake-up time from sleep mode is significantly higher

than that of standby mode, because time must be allowed for

the internal reference and common-mode buffers to re-enable and

to replenish charge to the internal capacitors. When returning to

normal mode, the specified wake-up time must be satisfied before

applying the first conversion start pulse. This specified time is the

time it takes from when the SPI command to exit the selected

power saving mode is written to the device configuration register

(see the Device Configuration Register section) to update the

OPERATING_MODES bits.

For the lowest power consumption in any of the power saving

operating modes, the LVDS_SELF_CLK_MODE must be enabled

in the ADC Data Interface Configuration B register (see the ADC

Data Interface Configuration B Register section) to power down the

LVDS DCO transmitter.

Table 11. Power Saving Operating Modes

Operating

Mode

OPERATING_MODES

Bits Value

Description

Effect

Wake-Up Time (Maximum Time to

Normal Mode)

Normal

0b00

Normal operating mode

Normal operation.

Not applicable

Standby

0b10

Standby operating mode

The internal IOVDD LDO regulator is disabled.

100μs

If IOVDD is not externally supplied, all GPIOx and all

LVDS data interface and SPI data interface signals

are disabled. For the SPI configuration interface only,

writes to the device configuration register (see the

Device Configuration Register section) and Interface

Configuration A register (see the Interface Configuration

A Register section) are allowed.

If IOVDD is externally supplied, all GPIOx and SPI data

interface signals are enabled. The SPI configuration

interface is fully enabled. Because the SPI data

interface remains enabled, the user can access data

in the result FIFO (see the Result FIFO section).

The ADC core is powered down. The analog circuitry

remains in reset (ANA_RESET remains asserted), and

no ADC conversions can be performed.

The VDD33 supply can be removed to reduce power.

When in use, the internal VDD11 LDO regulator remains

on.

The internal reference buffer is enabled.

The common-mode output buffer is enabled.

The LVDS interface is disabled.

Sleep

0b11

Low power operating mode

The internal IOVDD LDO regulator is disabled.

180μs

If IOVDD is not externally supplied, all GPIOx and all

LVDS and SPI data interface signals are disabled. For

the SPI configuration interface only, writes to the device

AD4083BBCZ Datasheet(PDF) 25 Page - Analog Devices

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