CY7C4255
CY7C4265
Document #: 38-06004 Rev. *C
Page 5 of 22
AC Test Loads and Waveforms[9, 10]
3.0V
5V
OUTPUT
R1 1.1 K
Ω
R2
680
Ω
CL
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤ 3ns
≤ 3 ns
OUTPUT
1.91V
Equivalent to:
THÉVENIN EQUIVALENT
410
Ω
ALL INPUT PULSES
Switching Characteristics Over the Operating Range
7C42X5-10
7C42X5-15
7C42X5-25
7C42X5-35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
tS
Clock Cycle Frequency
100
66.7
40
28.6
MHz
tA
Data Access Time
2
8
2
10
2
15
2
20
ns
tCLK
Clock Cycle Time
10
15
25
35
ns
tCLKH
Clock HIGH Time
4.5
6
10
14
ns
tCLKL
Clock LOW Time
4.5
6
10
14
ns
tDS
Data Set-Up Time
3
4
6
7
ns
tDH
Data Hold Time
0.5
1
1
2
ns
tENS
Enable Set-Up Time
3
4
6
7
ns
tENH
Enable Hold Time
0.5
1
1
2
ns
tRS
Reset Pulse Width[11]
10
15
25
35
ns
tRSR
Reset Recovery Time
8
10
15
20
ns
tRSF
Reset to Flag and Output Time
10
15
25
35
ns
tPRT
Retransmit Pulse Width
30
35
45
55
ns
tRTR
Retransmit Recovery Time
60
65
75
85
ns
tOLZ
Output Enable to Output in Low Z[12]
00
0
0
ns
tOE
Output Enable to Output Valid
3
7383
12
3
15
ns
tOHZ
Output Enable to Output in High Z[12]
3
7383
12
3
15
ns
tWFF
Write Clock to Full Flag
8
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tPAFasynch Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)
12
16
20
25
ns
tPAFsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
810
15
20
ns
tPAEasynch Clock to Programmable Almost-Empty Flag[13]
(Asynchronous mode, VCC/SMODE tied to VCC)
12
16
20
25
ns
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS)
810
15
20
ns
tHF
Clock to Half-Full Flag
12
16
20
25
ns
tXO
Clock to Expansion Out
6
10
15
20
ns
Notes:
9. CL = 30 pF for all AC parameters except for tOHZ.
10. CL = 5 pF for tOHZ.
11. Pulse widths less than minimum values are not allowed.
12. Values guaranteed by design, not currently tested.
13. tPAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E).
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