CY7C4255 datasheet(12/22 Pages) CYPRESS

12 / 22 page

CY7C4255

CY7C4265

Document #: 38-06004 Rev. *C

Page 12 of 22

Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))

Write Programmable Registers

Notes:

28. If a write is performed on this rising edge of the write clock, there will be Full

− (m − 1) words of the FIFO when PAF goes LOW.

29. PAF offset = m.

30. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of

RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.

Switching Waveforms (continued)

Note

tENH

WCLK

PAF

RCLK

tCLKH

tENS

FULL– M WORDS

IN FIFO

tCLKL

tENS

FULL– M + 1 WORDS

IN FIFO

tENH

tENS

tENH

tENS

tPAF

REN

WEN

WEN2

tSKEW3

tPAF synch

[26]

[30]

tENH

WCLK

tCLKH

tENS

tCLKL

PAE OFFSET

D0 –D17

WEN

tENS

PAF OFFSET

PAE OFFSET

tCLK

D0 – D11

tDS

tDH

CY7C4255 Datasheet(PDF) 12 Page - Cypress Semiconductor

CY7C4255 Datasheet(HTML) 12 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL