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CY29658
Document #: 38-07478 Rev. **
Page 4 of 7
IIL
Input Current, Low[6]
VIL = VSS
–
–
–100
µA
IIH
Input Current, High[6]
VIL = VDD
–
–
100
µA
IDDA
PLL Supply Current
AVDD only
–
–
7
mA
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
–
–
4
mA
IDD
Dynamic Supply Current
Outputs loaded @ 100 MHz
–
330
–
mA
CIN
Input Pin Capacitance
–
4
–
pF
ZOUT
Output Impedance
12
15
18
Ω
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C)
[7]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
fVCO
VCO Frequency
200
–
400
MHz
fin
Input Frequency
÷2 Feedback
100
–
200
MHz
÷4 Feedback
50
–
100
Bypass mode (BYPASS# = 0)
0
–
200
frefDC
Input Duty Cycle
40
–
60
%
VPP
Peak-Peak Input Voltage
LVPECL
500
–
1000
mV
VCMR
Common Mode Range[8]
LVPECL
1.2
–
VDD – 0.6
V
fMAX
Maximum Output Frequency
÷2 Output
100
–
200
MHz
÷4 Output
50
–
100
DC
Output Duty Cycle
45
–
55
%
tr, tf
Output Rise/Fall times
0.6V to 1.8V
0.1
–
1.0
ns
t(φ)
Propagation Delay (static phase
offset)
PCLK to FB_IN, same VDD
–200
–
225
ps
tPD
Propagation Delay (PLL and
divider bypass)
PCLK to Q0 – Q9
BYPASS# = 0
4.1
5.5
6.9
ns
tsk(O)
Output-to-Output Skew
–
–
150
ps
tPLZ, HZ
Output Disable Time
–
–
6
ns
tPZL, ZH
Output Enable Time
–
–
6
ns
BW
PLL Closed Loop Bandwidth
(–3dB)
÷2 Feedback
–
1.9 – 2.2
–
MHz
÷4 Feedback
–
1.8 – 2.1
–
tJIT(CC)
Cycle-to-Cycle Jitter
–
–
100
ps
tJIT(PER)
Period Jitter
–
–
75
ps
tJIT(φ)
I/O Phase Jitter
I/O same VDD
–
–
150
ps
tLOCK
Maximum PLL Lock Time
–
–
1
ms
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)
[7]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
fVCO
VCO Frequency
200
–
500
MHz
fin
Input Frequency
÷2 Feedback
100
–
200
MHz
÷4 Feedback
50
–
125
Bypass mode (BYPASS# = 0)
0
–
200
Notes:
7.
AC characteristics apply for parallel output termination of 50
Ω to V
TT. Parameters are guaranteed by characterization and are not 100% tested.
8.
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing
lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
DC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) (continued)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit