6 / 19 page
W311
Document #: 38-07703 Rev. **
Page 6 of 19
Byte 3: Control Register
Bit
Pin#
Name
Default
Description
Bit 7
--
Reserved
0
Reserved
Bit 6
7
SEL_48MHz
0
0 = Select 24 MHz as output
1 = Select 48 MHz as output (default).
Bit 5
6
48MHz
1
(Active/Inactive)
Bit 4
7
24_48MHz
1
(Active/Inactive)
Bit 3
9
PCI_F
1
(Active/Inactive)
Bit 2
27
AGP2
1
(Active/Inactive)
Bit 1
26
AGP1
1
(Active/Inactive)
Bit 0
23
AGP0
1
(Active/Inactive)
Byte 4: Watchdog Timer Register
Bit
Pin#
Name
Default
Description
Bit 7
-
PCI_Skew1
0
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
Bit 6
-
PCI_Skew0
0
These bits store the time-out value of the Watchdog
Timer. The scale of the timer is determine by the pre
scaler.
The timer can support a value of 150 ms to 4.8 sec
when the pre-scalar is set to 150 ms. If the pre-scaler
is set to 2.5 sec, it can support a value from 2.5 sec
to 80 sec.
When the Watchdog Timer reaches to “0”, it will set
the WD_To_STATUS bit and generate Reset if
RST_EN_WD is enabled
Bit 5
Bit 4
-
WD_TIMER4
1
Bit 3
-
WD_TIMER3
1
Bit 2
-
WD_TIMER2
1
Bit 1
-
WD_TIMER1
1
Bit 0
-
WD_TIMER0
1
0 = 150 ms
1 = 2.5 sec
Byte 5: Control Register 5
Bit
Pin#
Name
Default
Description
Bit 7
6
48Mhz_DRV
1
0 = Norm, 1 = High Drive
Bit 6
7
24_48MHz_DRV
1
0 = Norm, 1 = High Drive
Bit 5
44
APIC1
1
(Active/Inactive)
Bit 4
45
APIC0
1
(Active/Inactive)
Bit 3
-
Reserved
0
Reserved
Bit 2
-
Reserved
0
Reserved
Bit 1
47
REF1
1
(Active/Inactive)
Bit 0
48
REF0
1
(Active/Inactive)
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