W311
Document #: 38-07703 Rev. **
Page 16 of 19
PCI Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V
30
–
–
ns
tH
High Time
Duration of clock cycle above 2.4V
12
–
–
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
–
–
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
–
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
–
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
––
500
ps
tSK
Output Skew
Measured on rising edge at 1.5V
–
–
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1.5
–
4
ns
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
––
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
–30–
Ω
AGP Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V
15
–
–
ns
tH
High Time
Duration of clock cycle above 2.4V
5.25
–
–
ns
tL
Low Time
Duration of clock cycle below 0.4V
5.05
–
–
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
–
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
–
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
––
500
ps
tSK
Output Skew
Measured on rising edge at 1.5V
–
–
250
ps
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
––
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
–30
–
Ω
APIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Frequency generated from PCI divided by 2
PCI/2
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
Ω
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