AT25DF021A-DWFHT datasheet(34/59 Pages) RENESAS

34 / 59 page

DS-AT25DF021A-042 Rev. L

Page 34

8/7/23

AT25DF021A Datasheet

11.2 Active Status Interrupt

To simplify the readout of the RDY/BSY bit, the Active Status Interrupt command (25h) can be used. It is then not

necessary to continuously read the status register, it is sufficient to monitor the value of the SO line. If the SO line

is connected to an interrupt line on the host controller, the host controller can be in sleep mode until the SO line

indicates that the AT25DN021A is ready for the next command.

The RDY/BSY bit can be read at any time, including during an internally self-timed program or erase operation.

To enable the Active Status Interrupt command, the CS pin must first be asserted and the opcode of 25h must be

clocked into the device. For SPI Mode3, at least one dummy bit has to be clocked into the device after the last bit

of the opcode has been clocked in. (In most cases, this is most easily done by sending a dummy byte to the

device.) The value of the SI line after the opcode is clocked in is of no significance to the operation. For SPI Mode

0, this dummy bit (dummy byte) is not required.

The value of RDY/BSY is then output on the SO line, and is continuously updated by the device for as long as the

CS pin remains asserted. Additional clocks on the SCK pin are not required. If the RDY/BSY bit changes from 1 to

0 while the CS pin is asserted, the SO line changes from 1 to 0. (The RDY/BSY bit cannot change from 0 to 1

during an operation, so if the SO line already is 0, it does not change.)

Deasserting the CS pin stops the Active Status Interrupt operation and put the SO pin into a high-impedance

state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 27. Active Status Interrupt

RDY/BSY

OPCODE

High-Impedance

SCK

MSB

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AT25DF021A-DWFHT Datasheet(PDF) 34 Page - Renesas Technology Corp