AT25DF021A-DWFHT datasheet(48/59 Pages) RENESAS

48 / 59 page

DS-AT25DF021A-042 Rev. L

Page 48

8/7/23

AT25DF021A Datasheet

14. Power-On/Reset State

When power is first applied to the device, or when recovering from a reset condition, the output pin (SO) is in a

high-impedance state, and a high-to-low transition on the CSB pin is required to start a valid command. The SPI

mode (Mode 3 or Mode 0) is automatically selected on every falling edge of CSB by sampling the inactive clock

state.

14.1 Power-Up/Power-Down Voltage and Timing Requirements

During power-up, the device must not be READ for at least the minimum tVCSL time after the supply voltage

reaches the minimum VPOR level (VPOR min). While the device is being powered-up, the internal Power-On Reset

(POR) circuitry keeps the device in a reset mode until the supply voltage rises above the minimum VCC. During

this time, all operations are disabled, and the device does not respond to any commands.

If the first operation to the device after power-up is a program or erase operation, then the operation cannot be

started until the supply voltage reaches the minimum VCC level and an internal device delay has elapsed. This

delay is a maximum time of tPUW. After the tPUW time, the device is in the standby mode (if CSB is at logic high), or

active mode (if CSB is at logic low). For the case of Power-down then Power-up operation, or if a power

interruption occurs (such that VCC drops below VPOR max), the VCC of the Flash device must be maintained below

VPWD for at least the minimum specified TPWD time. This is to ensure the Flash device resets properly after a

power interruption.

Figure 38. Power-Up Timing

Table 15. Voltage and Timing Requirements for Power-Up/Power-Down

Symbol

Parameter

Min

Max

Units

VPWD

VCC for device initialization

1.0

TPWD

Minimum duration for device initialization

300

µs

TVCSL

Minimum VCC to chip select low time for Read command

µs

TVR

VCC rise time

500000

µs/V

VPOR

Power on reset voltage

1.45

1.6

TPUW

Power up delay time before Program or Erase is allowed

CC max

Max V

PWD

Time

PWD

PUW

Full Operation Permitted

VCSL

Read Operation

Permitted

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