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MPQ9840GL Datasheet(PDF) 22 Page - Monolithic Power Systems

Part # MPQ9840GL
Description  36V, 3.5A, Low IQ, Synchronous Step-Down Converter AEC-Q100 Qualified
PDF  34 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MPQ9840GL Datasheet(HTML) 22 Page - Monolithic Power Systems

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MPQ9840 – 36V, 3.5A, LOW IQ, SYNC STEP-DOWN CONVERTER, AEC-Q100
MPQ9840 Rev. 1.02
www.MonolithicPower.com
22
7/1/2020
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2020 MPS. All Rights Reserved.
BST to SW. An external circuit should provide
enough voltage headroom to facilitate charging.
When the HS-FET is on, VIN is about equal to
SW, so the bootstrap capacitor cannot be
charged.
At a higher duty cycle operation condition, the
time period available to the bootstrap charging
is less, so the bootstrap capacitor may not be
charged sufficiently. In case the external circuit
does not have sufficient voltage or time to
charge the bootstrap capacitor, extra external
circuitry can be used to ensure that the
bootstrap voltage is in the normal operation
region.
Low Dropout Operation (BST Refresh)
To improve dropout, the MPQ9840 is designed
to operate at close to 100% duty cycle for as
long as the BST to SW voltage is greater than
2.5V. When the voltage from BST to SW drops
below 2.5V, the HS-FET is turned off using an
under-voltage lockout (UVLO) circuit, which
allows the LS-FET to conduct and refresh the
charge on the BST capacitor. In DCM or PSM,
the LS-FET is forced on to refresh the BST
voltage.
Since the supply current sourced from the BST
capacitor is low, the HS-FET can remain on for
more switching cycles than are required to
refresh the capacitor, making the effective duty
cycle of the switching regulator high.
The effective duty cycle during the dropout of
the regulator is mainly influenced by the voltage
drops across the power MOSFET, inductor
resistance, low-side diode and printed circuit
board resistance.
Internal Regulator
Most of the internal circuitry is powered on by
the 5V internal regulator. This regulator takes
the VIN input and operates in the full VIN range.
When VIN is greater than 5V, the output of the
regulator is in full regulation. When VIN is lower
than 5V, the output degrades.
For better thermal performance, connect BIAS
to an external 5V source. VCC and the internal
circuit are powered by BIAS. Since there is an
internal diode between BIAS and the internal
circuit, float BIAS or connect BIAS to GND if it
is not being used.
Enable (EN) Control
EN is a digital control pin that turns the
regulator on and off. When EN is pulled below
its threshold voltage, the chip is put into the
lowest shutdown current mode. Pulling EN
above its threshold voltage turns on the part.
Do not float EN.
Programmable Frequency (FREQ)
The
MPQ9840
oscillating
frequency
is
programmed either by an external resistor
(RFREQ) from FREQ to ground or by a logic level
SYNC signal. The value of RFREQ can be
calculated with Equation (1):
FREQ
1.11
s
170000
R(kΩ)
f(kHz)
(1)
The chip can be synchronized to an external
clock ranging from 350kHz up to 2.5MHz
through FREQ/SYNC.
SYNC and PHASE
The internal oscillator frequency can be
synchronized to an external clock ranging from
350kHz up to 2.5MHz through SYNC. The
external clock should be at least 250kHz larger
than the RFREQ set frequency. Ensure that the
high amplitude of the SYNC clock is higher than
1.8V and the low amplitude is lower than 0.4V.
There is no pulse width requirement, but there
is always parasitic capacitance of the pad, so if
the pulse width is too short, a clear rising and
falling edge may not be seen due to the
parasitic capacitance. A pulse longer than
100ns is recommended in application.
PHASE is used when two or more MPQ9840
devices are in parallel with the same SYNC
clock. Pulling PHASE high forces the MPQ9840
to operate in-phase of the SYNC clock. Pulling
PHASE low forces the device to be 180° out-of-
phase of the SYNC clock. By setting different
voltages for PHASE, two devices can operate
180° out-of-phase to reduce the total input
current ripple, so a smaller input bypass
capacitor can be used (see Figure 3). The
PHASE rising threshold is about 2.5V with a
400mV hysteresis.



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