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M58LR256KC Datasheet(PDF) 39 Page - Numonyx B.V |
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M58LR256KC Datasheet(HTML) 39 Page - Numonyx B.V |
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39 / 108 page  M58LRxxxKC, M58LRxxxKD Configuration Register 39/108 6.7 Valid clock edge bit (CR6) The valid clock edge bit, CR6, configures the active edge of the Clock, K, during synchronous read operations. When the valid clock edge bit is Low (set to ’0’) the falling edge of the Clock is the active edge. When the valid clock edge bit is High (set to ’1’) the rising edge of the Clock is the active edge. 6.8 Wrap burst bit (CR3) The wrap burst bit, CR3, selects between wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16-word boundary (wrap) or overcome the boundary (no wrap). When the wrap burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’) the burst read does not wrap. 6.9 Burst length bits (CR2-CR0) The burst length bits set the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, WAIT is asserted for 1, 2 or 3 clock cycles, respectively, when the burst sequence crosses the first 16-word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 13: Burst type definition. CR14, CR5 and CR4 are reserved for future use. |
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