M58LR256KC datasheet(45/108 Pages) NUMONYX

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M58LRxxxKC, M58LRxxxKD

Read modes

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Read modes

Read operations can be performed in two different ways depending on the settings in the

Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read

operation is asynchronous. If the data output is synchronized with clock, the read operation

is synchronous.

The read mode and format of the data output are determined by the Configuration Register

(see Section 6: Configuration Register for details). All banks support both asynchronous

and synchronous read operations.

7.1

Asynchronous read mode

In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data

corresponding to the address latched, that is the memory array, Status Register, common

Flash interface or electronic signature depending on the command issued. CR15 in the

Configuration Register must be set to ‘1’ for asynchronous operations.

The device features an automatic standby mode. During asynchronous read operations,

after a bus inactivity of 150 ns, the device automatically switches to the automatic standby

mode. In this condition the power consumption is reduced to the standby value and the

outputs are still driven.

In asynchronous read mode, the WAIT signal is always de-asserted.

See Table 24: Asynchronous read AC characteristics and Figure 9: Asynchronous random

access read AC waveforms for details.

7.2

Synchronous burst read mode

In synchronous burst read mode the data is output in bursts synchronized with the clock. It is

possible to perform burst reads across bank boundaries.

Synchronous burst read mode can only be used to read the memory array. For other read

operations, such as read Status Register, read CFI and read electronic signature, single

synchronous read or asynchronous random access read must be used.

In synchronous burst read mode the flow of the data output depends on parameters that are

configured in the Configuration Register.

A burst sequence starts at the first clock edge (rising or falling depending on valid clock

edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip

Enable, whichever occurs last. Addresses are internally incremented and data is output on

each data cycle after a delay which depends on the X latency bits CR13-CR11 of the

Configuration Register.

The number of words to be output during a synchronous burst read operation can be

configured as 4 words, 8 words, 16 words or continuous (burst length bits CR2-CR0). The

data can be configured to remain valid for one or two clock cycles (data output configuration

bit CR9).

The order of the data output can be modified through the wrap burst bit in the Configuration

boundary (wrap) or overcome the boundary (no wrap).

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