M58LR256KC datasheet(17/108 Pages) NUMONYX

17 / 108 page

M58LRxxxKC, M58LRxxxKD

Bus operations

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3.5

Standby

Standby disables most of the internal circuitry allowing a substantial reduction of the current

consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power

consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,

independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH

during a program or erase operation, the device enters standby mode when finished.

3.6

Reset

During reset mode the memory is deselected and the outputs are high impedance. The

memory is in reset mode when Reset is at VIL. The power consumption is reduced to the

reset level, independently from the Chip Enable, Output Enable, or Write Enable inputs. If

Reset is pulled to VSS during a program or erase, this operation is aborted and the memory

content is no longer valid.

Table 4.

Bus operations(1)

X = ‘don't care’

Operation

WAIT(2)

WAIT signal polarity is configured using the Set Configuration Register command.

ADQ15-ADQ0

Bus Read

VIL

VIH

Data Output

Bus write

VIL

VIH

VIL

VIH

Data Input

Address Latch

VIL

VIH

XVIL

VIH

Address Input

Output Disable

VIL

VIH

Hi-Z

Standby

VIH

Hi-Z

Reset

VIL

Hi-Z

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