MSP3400C datasheet(13/73 Pages) MICRONAS

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MSP 3400C

PRELIMINARY DATA SHEET

MICRONAS INTERMETALL

Table 4–1: Several examples for recommended channel assignments for demodulator and audio processing part

Mode

MSPC Sound IF-

Channel 1 / FM2

MSPC Sound IF-

Channel 2 / FM1

FM-

Matrix

Channel

Select

Channel

Matrix

B/G-Stereo

FM2 (5.74 MHz): R

FM1 (5.5 MHz): (L+R)/2

B/G Stereo

Speakers: FM

Stereo

B/G-Bilingual

FM2 (5.74 MHz): Sound B

FM1 (5.5 MHz): Sound A

No Matrix

Speakers: FM

H.Phone : FM

Speakers: Sound A

H.Phone : Sound B

Sat-Mono

not used

FM (6.5 MHz): mono

No Matrix

Speakers: FM

Sound A

Sat-Stereo

7.20 MHz: R

7.02 MHz: L

No Matrix

Speakers: FM

Stereo

Sat-Bilingual

7.38 MHz: Sound C

7.02 MHz: Sound A

No Matrix

Speakers: FM

H.Phone : FM

Speakers: Sound A

H.Phone :Sound B=C

Sat High Dev.

Mode (e.g.

EutelSat)

don’t care

6.552 MHz

No Matrix

Speakers: FM

H.Phone : FM

Speakers: Sound A

H.Phone : Sound A

4.4. Audio PLL and Crystal Specifications

The MSP 3400C runs at 18.432 MHz. A detailed specifi-

cation of the required crystal for different packages and

master/slave applications can be found in Table 8.5.2.

The clock supply of the entire system depends on the

MSP 3400C operation mode:

1. FM-Stereo/I2S Master operation:

The system clock runs free on the crystal’s 18.432 MHz.

2. I2S Slave operation:

In this case, the system clock is synchronizing on the

I2S_WS signal, which is fed into the MSP 3400C

(Mode_Reg[3] = 1).

3. D2-MAC operation:

In this case, the system clock is locked to a synchroniz-

ing signal (DMA_SYNC) supplied by the D2-MAC chip

(Mode_Reg[0] = 1). The DMA and the AMU chips can be

driven by the MSP 3400C audio clock (AUD_CL_OUT).

Remark on using the crystal:

External capacitors at each crystal pin to ground are re-

quired. They are necessary for tuning the open-loop fre-

quency of the internal PLL and for stabilizing the fre-

quency in closed-loop operation. The higher the

capacitors, the lower the clock frequency results. The

nominal free running frequency should match the center

of the tolerance range between 18.433 and 18.431 MHz

as closely as possible. Due to different layouts of cus-

tomer PCBs, the matching capacitor size should be de-

fined in the application (see also Table 8.5.2.).

4.5. ADR Bus

To be able to process ADR, the MSPC has a special de-

signed interface to work together with DRP 3510A. To be

prepared for an upgrade to ADR with an additional DRP

board, the following lines of MSP 3400C should be pro-

vided on a feature connector:

– AUD_CL_OUT

–I2S_DA_IN1 or I2S_DA_IN2

–I2S_DA_OUT

–I2S_WS

–I2S_CLK

– S_CL = ADR_CL

– S_ID = ADR_WS

– S_DA_IN = ADR_DA

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