TDA7500A datasheet(28/40 Pages) STMICROELECTRONICS

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TDA7500A

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2C TIMING

Figure 16. Definition of Timing for the I

2C BUS.

SPDIF TIMING

Symbol

Parameter

Test Condition

Standard Mode

I2C BUS

Fast Mode

I2C BUS

Unit

Min.

Max.

Min.

Max.

FSCL

SCLl clock frequency

100

400

kHz

tBUF

Bus free between a STOP and

Start Condition

4.7

–

1.3

–

µs

tHD:STA

Hold time (repeated) START

condition. After this period, the

first clock pulse is generated

4.0

–

0.6

–

µs

tLOW

LOW period of the SCL clock

4.7

–

1.3

–

µs

tHIGH

HIGH period of the SCL clock

4.0

–

0.6

–

µs

tSU:STA

Set-up time for a repeated start

condition

4.7

–

0.6

–

µs

tHD:DAT

DATA hold time

–

0.9

µs

Rise time of both SDA and SCL

signals

Cb in pF

–

1000

20+

0.1Cb

300

Fall time of both SDA and SCL

signals

Cb in pF

–

300

20+

0.1Cb

300

tSU;STO

Set-up time for STOP condition

–

0.6

–

µs

tSU:DAT

Data set-up time

250

100

Capacitive load for each bus line

–

400

–

400

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

SPVL

AC input level

0.2

0.5

3.3

Vpp

SPIR

Input impedance

@ 1 kHz

–6–

Ω

SPHYS

Hysteresis of input

–

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