3

©2016-2023 Renesas Electronics Corporation

November 20, 2023

8P34S2108 Datasheet

16

QA1

Output

Differential output pair A1. LVDS interface levels.

17

nQA1

Output

Differential output pair A1. LVDS interface levels.

18

QA2

Output

Differential output pair A2. LVDS interface levels.

19

nQA2

Output

Differential output pair A2. LVDS interface levels.

20

QA3

Output

Differential output pair A3. LVDS interface levels.

21

nQA3

Output

Differential output pair A3. LVDS interface levels.

22

QA4

Output

Differential output pair A4. LVDS interface levels.

23

nQA4

Output

Differential output pair A4. LVDS interface levels.

24

VDDQA

Power

Power supply pin for the channel A outputs QA[0:7].

25

QA5

Output

Differential output pair A5. LVDS interface levels.

26

nQA5

Output

Differential output pair A5. LVDS interface levels.

27

QA6

Output

Differential output pair A6. LVDS interface levels.

28

nQA6

Output

Differential output pair A6. LVDS interface levels.

29

QA7

Output

Differential output pair A7. LVDS interface levels.

30

nQA7

Output

Differential output pair A7. LVDS interface levels.

31

QB0

Output

Differential output pair B0. LVDS interface levels.

32

nQB0

Output

Differential output pair B0. LVDS interface levels.

33

QB1

Output

Differential output pair B1. LVDS interface levels.

34

nQB1

Output

Differential output pair B1. LVDS interface levels.

35

QB2

Output

Differential output pair B2. LVDS interface levels.

36

nQB2

Output

Differential output pair B2. LVDS interface levels.

37

VDDQB

Power

Power supply pin for the channel B outputs QB[0:7].

38

QB3

Output

Differential output pair B3. LVDS interface levels.

39

nQB3

Output

Differential output pair B3. LVDS interface levels.

40

QB4

Output

Differential output pair B4. LVDS interface levels.

41

nQB4

Output

Differential output pair B4. LVDS interface levels.

42

QB5

Output

Differential output pair B5. LVDS interface levels.

43

nQB5

Output

Differential output pair B5. LVDS interface levels.

44

QB6

Output

Differential output pair B6. LVDS interface levels.

45

nQB6

Output

Differential output pair B6. LVDS interface levels.

46

QB7

Output

Differential output pair B7. LVDS interface levels.

47

nQB7

Output

Differential output pair B7. LVDS interface levels.

48

VDDQB

Power

Power supply pin for the channel B outputs QB[0:7].

ePad

GND_EPAD

Power

Exposed pad of package. Connect to ground.

[a] Pull-up (PU) and pull-down (PD) resistors are indicated in parentheses. Pull-up and pull-down refers to internal input resistors.

See

Table 5, DC Input Characteristics, for typical values.

Table 1. Pin Descriptions[a]

Number

Name

Type

Description