15

©2016-2023 Renesas Electronics Corporation

November 20, 2023

8P34S2108 Datasheet

VFQFPN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 9. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed

on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific

and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis

and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved

when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is

also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33 mm) with 1oz copper via barrel plating. This is desirable to

avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug

and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern.

Note: These recommendations are to be used as a guideline only. For further information, please refer to the application note on the

Surface Mount Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.

Figure 9. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

Case Temperature Considerations

This device supports applications in a natural convection environment which does not have any thermal conductivity through ambient air.

The printed circuit board (PCB) is typically in a sealed enclosure without any natural or forced air flow and is kept at or below a specific

temperature. The device package design incorporates an exposed pad (ePad) with enhanced thermal parameters which is soldered to

the PCB where most of the heat escapes from the bottom exposed pad. For this type of application, it is recommended to use the

junction-to-board thermal characterization parameter JB (Psi-JB) to calculate the junction temperature (TJ) and ensure it does not

exceed the maximum allowed junction temperature in the Absolute Maximum Rating table.

The junction-to-board thermal characterization parameter, JB, is calculated using the following equation:

TJ = TCB + JB x PD, where

TJ = Junction temperature at steady state condition in (°C).

TCB = Case temperature (Bottom) at steady state condition in (°C).

JB = Thermal characterization parameter to report the difference between junction temperature and the temperature of the board

measured at the top surface of the board.

PD = power dissipation (W) in desired operating configuration.