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8P34S2108NLGI Datasheet(PDF) 14 Page - Renesas Technology Corp

Part # 8P34S2108NLGI
Description  Dual 1:8 LVDS Output 1.8V / 2.5V Fanout Buffer
PDF  21 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

8P34S2108NLGI Datasheet(HTML) 14 Page - Renesas Technology Corp

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©2016-2023 Renesas Electronics Corporation
November 20, 2023
8P34S2108 Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90 and 132. The actual value
should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100
parallel resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection
issues, the components should be surface mounted and must be placed as close to the receiver as possible. Renesas offers a full line of
LVDS compliant devices with two types of output structures: current source and voltage source. The standard termination schematic as
shown in Figure 7 can be used with either type of output structure. Figure 8, which can also be used with both output types, is an optional
termination with center tap capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a
non-standard termination, it is recommended to contact Renesas and confirm if the output structure is current source or voltage source
type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude and common-mode input range should be
verified for compatibility with the output.
Figure 7. Standard LVDS Termination
Figure 8. Optional LVDS Termination



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