HT9B95B datasheet(10/32 Pages) HOLTEK

10 / 32 page

Rev. 1.10

November 25, 2015

HT9B95A/B/G

Functional Description

Power-On Reset

When the power is applied, the device is initialized

by an internal power-on reset circuit. The status of the

internal circuits after initialization is as follows:

• All common outputs are set to VSS.

• All segment outputs are set to VSS.

• LCD Driver Output Waveform: B-type inversion.

• Internal oscillator is selected.

• The 1/3 bias drive mode is selected.

• LCD bias generator is in an off state.

• LCD Display and internal oscillator are in off

states.

• Power save mode is set to normal current.

• Frame Frequency is set to 80Hz.

• Blinking function is switched off

Data transfers on the I2C-bus should be avoided for

1 ms following power-on to allow completion of the

reset action.

System Oscillator

The timing for the internal logic and the LCD drive

signals are generated by the internal oscillator. The

System Clock frequency (fSYS) determines the LCD

frame frequency. During initial system power on the

System Oscillator will be in the stop state.

Segment Driver Outputs

The LCD drive section includes up to 43 segment

outputs SEG0 ~ SEG42 which should be connected

directly to the LCD panel. The segment output signals

are generated in accordance with the multiplexed

common signals and with the data resident in the display

latch. The unused segment outputs should be left

open-circuit.

Column Driver Outputs

The LCD drive section includes up to 8 column

outputs COM0~COM7 which should be connected

directly to the LCD panel. The column output signals

are generated in accordance with the selected LCD

drive mode. The unused column outputs should be

left open-circuit if less than 8 column outputs are

required.

Address Pointer

The addressing mechanism for the display RAM is

implemented using the address pointer. This allows

the loading of an individual display data byte, or a

series of display data bytes, into any location of the

display RAM. The sequence commences with the ini-

tialization of the address pointer by the Display Data

Input command.

Display Memory – RAM Structure

The display RAM is static 39x8 bits RAM which

stores the LCD data. Logic “1” in the RAM bit-map

indicates the “on” state of the corresponding LCD

segment; similarly, logic 0 indicates the ‘off’ state.

The contents of the RAM data are directly mapped

to the LCD data. The first RAM column corresponds

to the segments operated with respect to COM0.

In multiplexed LCD applications the segment data

from 2nd to 7th column of the display RAM are time-

multiplexed with COM1 to COM7 respectively. The

following diagram is a data transfer format for I2C

interface.

MSB

LSB

SDA Data

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

LCD Display Output Data Transfer Format for I2C Bus

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