HT9B95B datasheet(14/32 Pages) HOLTEK

14 / 32 page

Rev. 1.10

November 25, 2015

HT9B95A/B/G

I2C Serial Interface

I2C Operation

The device supports I2C serial interface. The I2C bus

is for bidirectional, two-line communication between

different ICs or modules. The two lines are a serial

data line, SDA, and a serial clock line, SCL. Both

lines are connected to the positive supply via pull-up

resistors with a typical value of 4.7kΩ. When the bus

is free, both lines are high. Devices connected to the

bus must have open-drain or open-collector outputs

to implement a wired-or function. Data transfer is

initiated only when the bus is not busy.

Data Validity

The data on the SDA line must be stable during the

high period of the serial clock. The high or low state

of the data line can only change when the clock signal

on the SCL line is Low as shown in the diagram.

START and STOP Conditions

• A high to low transition on the SDA line while SCL

is high defines a START condition.

• A low to high transition on the SDA line while SCL

is high defines a STOP condition.

• START and STOP conditions are always generated

by the master. The bus is considered to be busy after

the START condition. The bus is considered to be

free again a certain time after the STOP condition.

• The bus stays busy if a repeated START (Sr) is

generated instead of a STOP condition. In some

respects, the START(S) and repeated START (Sr)

conditions are functionally identical.

SDA

SCL

SDA

SCL

START condition

STOP condition

Byte Format

Every byte put on the SDA line must be 8-bit long.

The number of bytes that can be transmitted per

transfer is unrestricted. Each byte has to be followed

by an acknowledge bit. Data is transferred with the

most significant bit, MSB, first.

SDA

SCL

ACK

3-8

ACK

Acknowledge

• Each bytes of eight bits is followed by one

acknowledge bit. This Acknowledge bit is a low

level placed on the bus by the receiver. The master

generates an extra acknowledge related clock

pulse.

• A slave receiver which is addressed must generate

an Acknowledge, ACK, after the reception of each

byte.

• The device that acknowledges must pull down the

SDA line during the acknowledge clock pulse so

that it remains stable low during the high period of

this clock pulse.

• A master receiver must signal an end of data to the

slave by generating a not-acknowledge, NACK,

bit on the last byte that has been clocked out of

the slave. In this case, the master receiver must

leave the data line high during the 9th pulse to not

acknowledge. The master will generate a STOP or

repeated START condition.

clock pulse for

acknowledgement

Data Output

by Transmitter

Data Outptu

by Receiver

SCL From

Master

acknowledge

not acknowledge

START

condition

Slave Addressing

• The slave address byte is the first byte received

following the START condition form the master

device. The first seven bits of the first byte make

up the slave address. The eighth bit defines a read

or write operation to be performed. When the R/W

bit is “1”, a read operation is selected. When the R/

W bit is “0”, a write operation is selected.

• The HT9B95 device address bits are “0111110”.

When an address byte is sent, the device compares

the first seven bits after the START condition. If

they match, the device outputs an Acknowledge on

the SDA line.

Slave Address

MSB

LSB

R/W

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