DIO1413/1414

Version 1.2, Sep 2024

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© 2024 DIOO MICROCIRCUITS CO., LTD.

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9.3.1.1. Interrupt mode

In the interrupt mode, the

_____

ALERT pin is asserted when any channel’s temperature measuring consecutively

out-of-limit (≥ High Limit or < Low Limit) conditions or fault conditions is detected for the programmed number of

times. The

_____

ALERT pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit

condition has been removed, the

_____

ALERT pin will remain asserted until the appropriate status bits are cleared.

The appropriate status bits include External faults status, High Limit status and Low Limit status bits, all of which

are read clear (see section 12.10).

The

_____

ALERT pin can be masked by setting the MASK_ALL bit or channel mask register. Once the

_____

ALERT pin

has been masked, it will be deasserted and remain deasserted until the MASK_ALL bit or channel mask register

is cleared by the user. No matter MASK_ALL bit or channel mask register is set or not, the status registers (see

secton 12.2) will be updated normally.

The

_____

ALERT pin can be used as an interrupt signal or as an SMBus Alert signal, which allows an SMBus client

to report an error condition to the host. One or more

_____

ALERT outputs can be hard-wired together.

9.3.1.2. Comparator mode

In the comparator mode, the

_____

ALERT pin will be asserted if any of the measured temperature exceeds the

programmed High Limit for the programmed number of times in a consecutive measurements. The

_____

ALERT pin

will remain asserted until all the measured temperatures drop below the High Limit minus the Therm Hysteresis.

In the comparator mode, the

_____

ALERT pin cannot be masked by MASK_ALL bit or channel mask register. The

corresponding High Limit status bits will not be cleared until the

_____

ALERT pin is deasserted. Once the

_____

ALERT

pin is deasserted, the High Limit status bits will be automatically cleared.

9.3.2.

______

THERM pin

The output of the

______

THERM/ADDR pin cannot be masked. When the temperature of any channel is consecutively

detected exceeding the programmed Therm Limit for the programmed number of consecutive measurements,

the

______

THERM /ADDR pin will be asserted. And the

______

THERM /ADDR pin will remain asserted until the measured

temperatures that cause a thermal over-temperature event drop below the programmed Therm Limit minus the

Therm Hysteresis, and no other channel’s measured temperature consecutively detected exceeding the

programmed Therm Limit for the programmed number of consecutive measurements.

When the

______

THERM/ADDR pin is asserted, both the register Therm Limit Status bits (see section 12.8) and Status

bits (see section 12.2) will be set. These bits are not read clear and will only be clear when the

______

THERM/ADDR

pin is deasserted.

9.4. Open and short faults

Before monitoring the temperature on each external channel, the DIO1413/1414 check whether the BJT on the

external channel is properly connected to the DPx and DNx ports. The following two connections are considered

to be faults:



DP1 to DN1 or DP2 to DN2 (or DP2/DN3 to DN2/DP3 for DIO1414) is open;



DP1, or DP2, or DN2, or DN2 (or DP2/DN3 to DN2/DP3 for DIO1414) is short to VDD.