AS3722 datasheet(149/199 Pages) AMSOSRAM

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Page 148

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[v1-01] 2015-Sep-07

AS3722 − Register Description

Figure 164:

CTRLsequ1

Addr:58h

CTRLsequ1

Bit

Bit Name

Default

Access

Bit Description

ac_ok_pwr_on

RW_SS

Enables exit out of PWR OFF mode with pin

AC_OK (pin enabled in PWR off mode)

0 : AC_OK disabled

1 : AC_OK enabled

lid_pwr_on

RW_SS

Enables exit out of PWR OFF mode with pin LID

(pin enabled in PWR off mode)

0 : LID disabled

1 : LID enabled

2therm_inv

RW_SS

Sets the polarity of the THERM pin

0 : High active for THERM event

1 : Inverted: Low active for THERM event

3enable2_inv

RW_SS

Sets the polarity of the ENABLE2 pin

0 : High active for ENALBE2

1 : Inverted: Low active for ENABLE2

enable1_inv

Sets the polarity of the ENABLE1 pin

0 : High active for ENABLE1

1 : Inverted: Low active for ENABLE1

enable1_deepsleep

ENABLE1 signal enable for controlling

deepsleep/stand_by

0 : ENABLE1 signal not used for stand_by

entry/exit

1 : ENABLE1 signal used for stand_by entry/exit

onkey_nodebounce

Sets the debounce on ONKEY

0 : debounce on

1 : debounce off

7enable3_inv

RW_SS

Sets the polarity of the ENABLE3 pin

0 : High active for ENABLE3

1 : Inverted: Low active for ENABLE3

AS3722 Datasheet(PDF) 149 Page - ams-OSRAM AG

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