AS3722 datasheet(153/199 Pages) AMSOSRAM

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[v1-01] 2015-Sep-07

AS3722 − Register Description

Figure 170:

OC_pg_ctrl2

Figure 171:

CTRLstatus

Addr:5eh

OC_pg_ctrl2

Bit

Bit Name

Default

Access

Bit Description

N/A, has to be set to “0”

2:1

pg_vmask_time

Mask pwrgood_sd0 (=sd0_lv) and ovcurr

after voltage change (DVS)

0 : no masking

1 : 4us

2 : 8us

3 : do not use

5:3

pg_sd6_ovc_alarm

Selects overcurrent alarm threshold of

dcdc6 per phase

0 : disabled

1 : 1.6A

2 : 1.8A

3 : 2.0A

4 : 2.2A

5 : 2.4A

6 : 2.6A

7 : 2.8A

pg_pwrgood_sd6_mask

Mask power good for dcdc6 (dcdc6_lv)

signal on selected GPIO output

7pg_ovcurr_sd6_mask

Mask overcurrent alarm threshold of

dcdc6 on selected GPIO output

if bits 7 and 6 are 0, pg_sd6 (if selected as

GPIO out function) represents power good

and overcurrent

function of sd6

Addr:5fh

CTRLstatus

Bit

Bit Name

Default

Access

Bit Description

ac_ok

Status of AC_OK pin

1lid

Status of LID pin

therm

Status of THERM pin

ov_curr

Over current of SD0 reached

4enable1

Status of enable1 signal (enable1 XOR

enable1_inv)

AS3722 Datasheet(PDF) 153 Page - ams-OSRAM AG

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