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AS3722 Datasheet(PDF) 152 Page - ams-OSRAM AG

Part # AS3722
Description  Multi-Phase DCDC Controller PMIC
PDF  199 Pages
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Manufacturer  AMSOSRAM [ams-OSRAM AG]
Direct Link  https://ams-osram.com/
Logo AMSOSRAM - ams-OSRAM AG

AS3722 Datasheet(HTML) 152 Page - ams-OSRAM AG

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ams Datasheet
Page 151
[v1-01] 2015-Sep-07
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AS3722 − Register Description
Figure 168:
SDlv_deb
Figure 169:
OC_pg_ctrl
Addr:5ch
SDlv_deb
Bit
Bit Name
Default
Access
Bit Description
7:6
pg_sd6_vmask_time
0
RW
Mask pwrgood_sd6 (=sd6_lv) and ovcurr after
voltage change (DVS)
0 : no masking
1 : 4us
2 : 8us
3 : do not use
5:4
sd6_lv_deb
0
RW
Selects debounce time of sd6_lv signal
0 : no debouncing
1 : 1 us
2 : 4 us
3 : 20 us
3:2
sd1_lv_deb
0
RW
Selects debounce time of sd1_lv signal
0 : no debouncing
1 : 1 us
2 : 4 us
3 : 20 us
1:0
sd0_lv_deb
0
RW
Selects debounce time of sd0_lv signal
0 : no debouncing
1 : 1 us
2 : 4 us
3 : 20 us
Addr:5dh
OC_pg_ctrl
Bit
Bit Name
Default
Access
Bit Description
0
pg_ac_ok_inv
0
RW
Invert AC_OK for OC_PG signal
1
pg_ac_ok_mask
0
RW
Mask AC_OK for OC_PG signal
2
pg_gpio3_mask
0
RW
Mask gpio3 for OC_PG signal
3
pg_gpio4_mask
0
RW
Mask gpio4 for OC_PG signal
4
pg_gpio5_mask
0
RW
Mask gpio5 for OC_PG signal
5
pg_pwrgood_sd0_mask
0
RW
Mask pwrgood for OC_PG signal
power good is the sd0_lv signal
6
pg_ovcurr_sd0_mask
0
RW
Mask ovc_alarm threshold of SD0
7
pg_vresfall_mask
0
RW
Mask ResVoltFall (alarm threshold)



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