Table 8-1. Switching Frequency and Compensation

COMPENSATION

RCF

SWITCHING

FREQUENCY

MINIMUM OUTPUT

CAPACITANCE FOR

VOUT < 1V

MINIMUM OUTPUT

CAPACITANCE FOR

1V ≤ VOUT < 3.3V

MINIMUM OUTPUT

CAPACITANCE FOR

VOUT ≥ 3.3V

for smallest output

capacitance

(comp setting 1)

RCF(kΩ)=18MHz×kΩ

fS(MHz) 1.8MHz(10kΩ)...

4MHz (4.5kΩ)

53µF

32µF

27µF

for medium output

capacitance

(comp setting 2)

RCF(kΩ)=60MHz×kΩ

fS(MHz) 1.8MHz(33kΩ)...

4MHz (15kΩ)

100µF

60µF

50µF

for large output

capacitance

(comp setting 3)

RCF(kΩ)=180MHz×kΩ

fS(MHz) 1.8MHz(100kΩ)...

4MHz (45kΩ)

200µF

120µF

100µF

for smallest output

capacitance

(comp setting 1)

tied to GND

internally fixed

2.25MHz

53µF

32µF

27µF

for large output

capacitance

(comp setting 3)

tied to VIN

internally fixed

2.25MHz

200µF

120µF

100µF

Refer to Section 9.2.2.5 for further details on the output capacitance required depending on the output voltage.

All values are the effective value of capacitance.

A too high resistor value for RCF is read as "tied to VIN", and a value below the lowest range as "tied to

GND". The minimum output capacitance in Table 8-1 is for capacitors close to the output of the device. If the

capacitance is distributed, a lower compensation setting can be required.

8.3.4 MODE/SYNC

When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current.

The MODE/SYNC pin forces PWM mode when set high. The pin also allows you to apply an external clock in

a frequency range from 1.8MHz to 4MHz for external synchronization. When an external clock is applied, the

device operates in PWM mode. As with the switching frequency selection, the specification for the minimum

on-time has to be observed when applying the external clock signal. When using external synchronization, TI

recommends to set the switching frequency as set by RCF to a similar value as the externally applied clock. This

ensures that the switching frequency stays in the same range when the external clock fails and the settling time

to the internal clock is reduced. When there is no resistor from COMP/FSET to GND, but the pin is pulled high

or low, external synchronization is not possible. An internal PLL allows you to change from an internal clock

to external clock during operation. The synchronization to the external clock is done on the falling edge of the

applied clock to the rising edge of the internal SW pin. The MODE/SYNC pin can be changed during operation.

See Section 9.3.2 for more details.

8.3.5 Spread Spectrum Clocking (SSC) - TPSM8281xS

These devices offer spread spectrum clocking, where the switching frequency is randomly changed in

PWM mode when the internal clock is used. The frequency variation is typically between the nominal

switching frequency and up to 288kHz above the nominal switching frequency. When the device is externally

synchronized, the TPSM8281xS follows the external clock and the internal spread spectrum block is turned off.

SSC is also disabled during soft start.

8.3.6 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off both the

MOSFETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if the input

voltage goes below the falling threshold.

8.3.7 Power-Good Output (PG)

The device has a power good output with window comparator. The PG pin goes high impedance after the FB

pin voltage is above 95% and less than 107% of the nominal voltage, and is driven low after the voltage falls

below typically 90% or higher than 110% of the nominal voltage. Table 8-2 shows the typical PG pin logic. The

PG pin is an open-drain output and is specified to sink up to 2mA. The power good output requires a pullup

TPSM82810, TPSM82813

SLUSDN6D – SEPTEMBER 2019 – REVISED JUNE 2026

www.ti.com

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