RX72N datasheet(115/179 Pages) RENESAS

115 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 115 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.6

EXDMAC Timing

Figure 2.32

EDREQ0 and EDREQ1 Input Timing

Figure 2.33

EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)

Figure 2.34

EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM)

Table 2.27

EXDMAC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = 8 to 240 MHz, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, BCLK = SDCLK = 8 to 80 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit

Test Conditions

EXDMAC

EDREQ setup time

tEDRQS

—

Figure 2.32

EDREQ hold time

tEDRQH

2—

EDACK delay time

tEDACD

—

Figure 2.33,

Figure 2.34

BCLK pin

tEDRQS tEDRQH

EDREQ0,

EDREQ1

EDACK0,

EDACK1

tEDACD

BCLK pin

tEDACD

EDACK0,

EDACK1

tEDACD

BCLK pin

tEDACD

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