RX72N datasheet(118/179 Pages) RENESAS

118 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 118 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.3

TMR

Note 1. tPBcyc: PCLKB cycle

Figure 2.38

TMR Clock Input Timing

2.4.7.4

CMTW

Note 1. tPBcyc: PCLKB cycle

Figure 2.39

CMTW Input Capture Input Timing

Table 2.30

TMR Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

TMR

Timer clock pulse width

Single-edge setting

tTMCWH,

tTMCWL

1.5

—

tPBcyc

Figure 2.38

Both-edge setting

2.5

—

Table 2.31

CMTW Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

CMTW

Input capture input pulse

width

Single-edge setting

tCMTWTICW

1.5

—

tPBcyc

Figure 2.39

Both-edge setting

2.5

—

PCLKB

TMCI0 to TMCI3

tTMCWL

tTMCWH

Input capture

input

PCLKB

tCMTWICW

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