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RX72N Datasheet(PDF) 131 Page - Renesas Technology Corp |
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RX72N Datasheet(HTML) 131 Page - Renesas Technology Corp |
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131 / 179 page  R01DS0343EJ0120 Rev.1.20 Page 131 of 179 Nov 15, 2023 RX72N Group 2. Electrical Characteristics 2.4.7.10 RIIC Table 2.39 RIIC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, High-drive output is selected by the drive capacity control register. Item Symbol Min.*1 Max. Unit Test Conditions RIIC (Standard-mode, SMBus) ICFER.FMPE = 0 SCL input cycle time tSCL 6(12) × tIICcyc + 1300 — ns Figure 2.62 SCL input high pulse width tSCLH 3(6) × tIICcyc + 300 — ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rise time tSr —1000 ns SCL, SDA input fall time tSf —300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 1000 — ns Stop condition input setup time tSTOS 1000 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0— ns SCL, SDA capacitive load Cb*2 — 400 pF RIIC (Fast-mode) ICFER.FMPE = 0 SCL input cycle time tSCL 6(12) × tIICcyc + 600 — ns SCL input high pulse width tSCLH 3(6) × tIICcyc + 300 — ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rise time tSr 20 × (External pull-up voltage/5.5V) 300 ns SCL, SDA input fall time tSf 20 × (External pull-up voltage/5.5V) 300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 300 — ns Stop condition input setup time tSTOS 300 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0— ns SCL, SDA capacitive load Cb*2 — 400 pF RIIC (Fast-mode+) ICFER.FMPE = 1 SCL input cycle time tSCL 6(12) × tIICcyc + 240 — ns SCL input high pulse width tSCLH 3(6) × tIICcyc + 120 — ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 120 — ns SCL, SDA input rise time tSr —120 ns SCL, SDA input fall time tSf —120 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 120 — ns Start condition input hold time tSTAH tIICcyc + 120 — ns Restart condition input setup time tSTAS 120 — ns Stop condition input setup time tSTOS 120 — ns Data input setup time tSDAS tIICcyc + 20 — ns Data input hold time tSDAH 0— ns SCL, SDA capacitive load Cb*2 — 550 pF |
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