RX72N datasheet(133/179 Pages) RENESAS

133 / 179 page

R01DS0343EJ0120 Rev.1.20

Page 133 of 179

Nov 15, 2023

RX72N Group

2. Electrical Characteristics

2.4.7.11

RSPI

Note 1. tPAcyc: PCLKA cycle

Note 2. We recommend using pins that have a letter (“-A”, “-B”, etc.) to indicate group membership appended to their names as groups.

For the RSPI interface, the AC portion of the electrical characteristics is measured for each group.

Table 2.40

RSPI Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the drive capacity control register.

Item

Symbol

Min.*1

Max.*1

Unit*1

Test

Conditions*2

RSPI

RSPCK clock cycle

Master

tSPcyc

2—

tPAcyc Figure 2.63

Slave

—

RSPCK clock high pulse

width

Master

tSPCKWH

(tSPcyc – tSPCKr

– tSPCKf) / 2 – 3

—ns

Slave

(tSPcyc – tSPCKr

– tSPCKf) / 2

—

RSPCK clock low pulse

width

Master

tSPCKWL

(tSPcyc – tSPCKr

– tSPCKf) / 2 – 3

—ns

Slave

(tSPcyc – tSPCKr

– tSPCKf) / 2

—

RSPCK clock rise/fall time

Output

tSPCKr,

tSPCKf

—5

Input

—

µs

Data input setup time

Master

tSU

—

Figure 2.64 to

Figure 2.69

Slave

8.3

—

Data input hold time

Master PCLKA divi-

sion ratio set to

1/2

tHF

0—

PCLKA divi-

sion ratio set to

a value other

than 1/2

tPAcyc

—

Slave

8.3

—

SSL setup time

Master

tLEAD

tSPcyc

Slave

—

tPAcyc

SSL hold time

Master

tLAG

tSPcyc

Slave

—

tPAcyc

Data output delay time

Master

tOD

—6.3

Slave

—

Data output hold time

Master

tOH

0—

Slave

—

Successive transmission

delay time

Master

tTD

tSPcyc + 2 × tPAcyc

8 × tSPcyc

+ 2 × tPAcyc

Slave

6 × tPAcyc

—

MOSI and MISO

rise/fall time

Output

tDr, tDf

—5

Input

—

µs

SSL

rise/fall time

Output

tSSLr,

tSSLf

—5

Input

—

µs

Slave access time

tSA

—2 × tPAcyc

+ 28

Figure 2.68,

Figure 2.69

Slave output release time

tREL

—2 × tPAcyc

+ 28

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