R5F572MDDDFB datasheet(5/180 Pages) RENESAS

5 / 180 page

RX72M Group

1. Overview

R01DS0332EJ0120 Rev.1.20

Page 5 of 180

Nov 15, 2023

DMA

DMA controller

(DMACAa)

 8 channels

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Activation sources: Software trigger and interrupt requests from peripheral functions

EXDMA controller

(EXDMACa)

 2 channels

Four transfer modes: Normal transfer, repeat transfer, block transfer, and cluster

transfer

 Single-address transfer enabled with the EDACKn signal

 Request sources: Software trigger, external DMA requests (EDREQn), and interrupt

requests from peripheral functions

Data transfer controller

(DTCb)

 Three transfer modes: Normal transfer, repeat transfer, and block transfer

 Request sources: External interrupts and interrupt requests from peripheral functions

 Sequence transfer

I/O ports

Programmable I/O ports

 I/O ports for the 224-pin LFBGA

I/O pins: 182

Input pin: 1

Pull-up resistors: 182

Open-drain outputs: 182

5-V tolerance: 19

 I/O ports for the 176-pin LFBGA and 176-pin LFQFP

I/O pins: 136

Input pin: 1

Pull-up resistors: 136

Open-drain outputs: 136

5-V tolerance: 19

 I/O ports for the 144-pin LFQFP

I/O pins: 111

Input pin: 1

Pull-up resistors: 111

Open-drain outputs: 111

5-V tolerance: 17

 I/O ports for the 100-pin LFQFP

I/O pins: 72

Input pin: 1

Pull-up resistors: 72

Open-drain outputs: 72

5-V tolerance: 12

Event link controller (ELC)

 Event signals such as interrupt request signals can be interlinked with the operation of

functions such as timer counting, eliminating the need for intervention by the CPU to

control the functions.

 137 internal event signals can be freely combined for interlinked operation with

connected functions.

 Event signals from peripheral modules can be used to change the states of output pins

(of ports B and E).

 Changes in the states of pins (of ports B and E) being used as inputs can be interlinked

with the operation of peripheral modules.

Table 1.1

Outline of Specifications (4/11)

Classification

Module/Function

Description

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