RZSLASHG2M datasheet(143/169 Pages) RENESAS

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RZ/G Series, 2nd Generation Datasheet

Section 3. Electrical Characteristics

R01DS0483EJ0101 Rev.1.01

Page 143 of 169

Jun 30, 2025

3.32 DBSC4 Access Timing

Table 3.32.1 DBSC4 Access Timing (DDR3L) [RZ/G2E]

Conditions for DDR3L: VDDQ_DDR = 1.35 V + 0.100/-0.067 V, GND = VSS = 0 V, Ta = -40 to +85 C,

Tj = -40 to +115 C

MDQ, MDQS, MDQS#, and MDM pins = output driver 34Ω setting, other pins = output driver

40Ω setting

Item

Symbol

Min.

Max.

Unit

Figures

MCK average clock period

tCK(avg)

1.074

1.266

Figure 3.32.2

MCK absolute high pulse width

tCH(abs)

0.44

—

tCK(avg)

Figure 3.32.2

MCK absolute low pulse width

tCL(abs)

0.44

—

tCK(avg)

Figure 3.32.2

Command, Address, and Control output setup

time to MCK, MCK#

tOS(1T)

310

—

Figure 3.32.3

tOS(2T)

890

—

Command, Address, and Control output hold

time from MCK, MCK#

tOH(1T)

310

—

Figure 3.32.3

tOH(2T)

320

—

Command, Address, and Control pulse width

for each output

tOPW(1T)

620

—

Figure 3.32.3

tOPW(2T)

1210

—

Write Latency

CWL

—

tCK(avg)

Figure 3.32.4

MDQS, MDQS# rising edge to MCK, MCK#

rising edge (write)

tWDQSS

-0.20

0.20

tCK(avg)

Figure 3.32.4

MDQS, MDQS# falling edge setup time to

MCK, MCK# rising edge (write)

tWDSS

0.25

—

tCK(avg)

Figure 3.32.4

MDQS, MDQS# falling edge hold time from

MCK, MCK# rising edge (write)

tWDSH

0.25

—

tCK(avg)

Figure 3.32.4

MDQS, MDQS# differential high pulse width

(write)

tWDQSH

0.45

0.55

tCK(avg)

Figure 3.32.5

MDQS, MDQS# differential low pulse width

(write)

tWDQSL

0.45

0.55

tCK(avg)

Figure 3.32.5

MDQS, MDQS# differential WRITE Preamble

(write)

tWPRE

0.9

—

tCK(avg)

Figure 3.32.5

MDQS, MDQS# differential WRITE

Postamble (write)

tWPST

0.3

—

tCK(avg)

Figure 3.32.5

MDQ and MDM output setup time to MDQS,

MDQS# (write)

tWDS

167

—

Figure 3.32.6

MDQ and MDM output hold time from DQS,

DQS# (write)

tWDH

167

—

Figure 3.32.6

MDQ and MDM output pulse width for each

output (write)

tWDIPW

334

—

Figure 3.32.6

Read latency

—

tCK(avg)

Figure 3.32.7

MDQS, MDQS# rising edge input access time

from rising MCK, MCK# (read)

tRDQSCK

-225

1375

Figure 3.32.7

MDQS, MDQS# differential input high pulse

width (read)

tRQSH

0.4

—

tCK(avg)

Figure 3.32.8

RZ/G2M V1.3

RZ/G2N

RZ/G2E

RZ/G2M V3.0

RZ/G2H

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