RZSLASHG2N datasheet(8/169 Pages) RENESAS

8 / 169 page

RZ/G Series, 2nd Generation Datasheet

Section 1 Overview

R01DS0483EJ0101 Rev.1.01

Page 8 of 169

Jun 30, 2025

Item

Description

Boot

(For All Products)

• System startup with selectable boot mode at power-on reset

• Either external ROM boot (area 0) or on-chip ROM boot can be selected through MD pin

on development chip.

• In on-chip ROM boot, RPC-IF or QSPI serial ROM boot is supported.

• Program downloaded to internal memory (System RAM)

• Autorun function for the downloaded program

• About detail information of BOOT, refer to Section 24 (Boot) and Appendix B (Active

sequence).

Direct Memory Access

Controller for Audio

(Audio-DMAC)

(For All Products)

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N

• 32 channels

• asdm0: 16 channels

• asdm1: 16 channels

RZ/G2E

• 16 channels

• asdm0: 16 channels

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N RZ/G2E

• Address space: 4 GBytes on architecture

• Data transfer length: Byte, word (2 Bytes), longword (4 Bytes), 8 Bytes, 16 Bytes, 32 Bytes

and 64 Bytes

• Maximum number of transfer times: 16,777,215 times

• Transfer request:

Selectable from on-chip peripheral module request and auto request

• Bus mode:

Selectable from normal mode and slow mode

• Priority: Selectable from fixed channel priority mode and round-robin mode

• Interrupt request: Supports interrupt request to CPU at the end of data transfer

• Repeat function: Automatically resets the transfer source, destination, and count at the

end of DMA transfer (by descriptor function)

• Descriptor function (each channel) supported

• MMU (each channel) supported

• Channel bandwidth arbiter (each channel)

Audio-DMAC-

Peripheral-Peripheral

(For All Products)

• Audio-DMAC (for transfer from Peripheral to Peripheral)

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N

• 29 channels + 29 (extended) channels for audio domain

RZ/G2E

• 29 (extended) channels for audio domain

RZ/G2H RZ/G2M V1.3 RZ/G2M V3.0 RZ/G2N

• Data transfer length: longword (4 Bytes)

• Transfer count: Transfer count is not specified (DMA transfer is made from the transfer-

start to transfer-stop settings.).

• Transfer request:

Selectable from on-chip audio peripheral module request

• Priority: round-robin mode

• Interrupt request: not supports interrupt request to CPU at the end of data transfer

IPMMU

(For All Products)

• An IPMMU is a memory management unit (MMU) which provides address translation and

access protection functionalities to processing units and interconnect networks.

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