RZSLASHG2E datasheet(107/169 Pages) RENESAS

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RZ/G Series, 2nd Generation Datasheet

Section 3. Electrical Characteristics

R01DS0483EJ0101 Rev.1.01

Page 107 of 169

Jun 30, 2025

Table 3.16.4 Ethernet Control Timing (RGMII Rx clock internal Delay Mode)

Conditions: VDDQ25_ETH = 2.5 ± 0.1 V [RZ/G2H, RZ/G2M V1.3, RZ/G2M V3.0, RZ/G2N],

VDDQ25_AVB0 = 2.5 ± 0.2 V [RZ/G2E],

Tc = -40 to +115 °C [RZ/G2H, RZ/G2M V1.3],

Ta = -40 to +85 °C [RZ/G2M V3.0, RZ/G2N, RZ/G2E],

Tj = -40 to +115 °C [RZ/G2M V3.0, RZ/G2N, RZ/G2E], GND = VSS = 0 V, CL = 30 pF

Item

Symbol

Min.

Typ.

Max.

Unit

Figures

AVB_RXC cycle time *

Tcyc

7.2

8.8

—

AVB_RXC duty cycle (in 1 Gbps)

Duty_G

AVB_RXC duty cycle (in 100 Mbps)

Duty_T

AVB_RX_CTL to clock input skew

TskewR

-500

500

Figure 3.16. 6

AVB_RD[3:0] to clock input skew

TskewR

-500

500

Note:

* For 100 Mbps, Tcyc will scale to 40 ns ± 4 ns respectively.

Figure 3.16.6 RGMII Delay Mode Reception Timing

AVB_RXC

AVB_RD[3:0]

AVB_RX_CTL

RD[3:0]

RD[7:4]

RD[3:0]

RXDV

RXERR

TskewR

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